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Mark R. Hartoog

Bio: Mark R. Hartoog is an academic researcher from VLSI Technology. The author has contributed to research in topics: Integrated circuit & Routing (electronic design automation). The author has an hindex of 10, co-authored 11 publications receiving 371 citations.

Papers
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Patent
01 May 1995
TL;DR: In this paper, a topology manager compacts the circuit topology while at the same time optimizing the routing of the interconnections among the circuit elements, standard cells and/or cell blocks of the circuit design.
Abstract: An automated routing tool for routing interconnections between circuit elements, standard cells and/or cell blocks of cell-based designs which incorporates the best features of both currently known gate array routing techniques with currently known cell-based routing techniques. The invention eliminates the disadvantages of permitting the detailed router to adjust the relative positions of the circuit elements, standard cells and/or cell blocks during the detailed routing process. The method employs a topology manager which iteratively compacts the circuit topology while at the same time optimizing the routing of the interconnections among the circuit elements, standard cells and/or cell blocks of the circuit design. The method employs bin-based global routing, which identifies expandable boundaries and which provides input to a compaction routine which expands or contracts the expandable areas in accordance with the result of the global routing process. The detailed routing step is not performed until after the relative positions of the circuit elements, cells and/or cell blocks have been already fixed.

73 citations

Patent
14 Oct 1994
TL;DR: In this article, the authors present a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees.
Abstract: The present invention discloses a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees. The invention includes developing a set of circuit specifications including maximum clock skew, minimum driveability, and maximum ramp delay. These specifications are described in a hardware description language on a digital computer system, and a netlist is synthesized from this hardware description. A modified netlist is then formed by analyzing the netlist and inserting buffers into it to satisfy the circuit specifications of skew, driveabilility, and ramp delay. Thereafter, a digital integrated circuit is produced as specified by the modified netlist.

47 citations

Patent
30 May 1997
TL;DR: In this article, the authors present a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees.
Abstract: The present invention discloses a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees. The invention includes developing a set of circuit specifications including maximum clock skew, minimum driveability, and maximum ramp delay. These specifications are described in a hardware description language on a digital computer system, and a netlist is synthesized from this hardware description. A modified netlist is then formed by analyzing the netlist and inserting buffers into it to satisfy the circuit specifications of skew, driveability, and ramp delay. Thereafter, a digital integrated circuit is produced as specified by the modified netlist.

47 citations

Proceedings ArticleDOI
Mark R. Hartoog1
02 Jul 1986
TL;DR: It is found that the Min Cut partitioning with simplified Terminal Propagation is the most efficient placement procedure studied and mean results of many placements should be used when comparing algorithms.
Abstract: This paper describes a study of placement procedures for VLSI Standard Cell Layout. The procedures studied are Simulated Annealing, Min Cut placement, and a number of improvements to Min Cut placement including a technique called Terminal Propagation which allows Min Cut to include the effect of connections to external cells. The Min Cut procedures are coupled with a Force Directed Pairwise Interchange (FDPI) algorithm for placement improvement. For the same problem these techniques produce a range of solutions with a typical standard deviation 4% for the total wire length and 3% to 4% for the routed area. The spread of results for Simulated Annealing is even larger. This distribution of results for a given algorithm implies that mean results of many placements should be used when comparing algorithms. We find that the Min Cut partitioning with simplified Terminal Propagation is the most efficient placement procedure studied.

39 citations

Patent
25 Sep 1992
TL;DR: Flexible routing of gate arrays increases routing efficiency, provides for the routing of functional blocks with other gates in the gate array, and provides structures for flexible power routing, particularly of gate array having functional blocks as mentioned in this paper.
Abstract: Flexible routing of gate arrays increases routing efficiency, provides for the routing of functional blocks with other gates in the gate array, and provides structures for flexible power routing, particularly of gate arrays having functional blocks. In particular, a gate-array-implemented integrated circuit is designed using a computer by representing in computer memory a gate array base, placing gate array cells on the gate array base in placement rows each having a uniform height and separated by routing channels in which no gate array cells are placed, and routing in the routing channel connections between placement rows according to a netlist, during routing increasing the size of a routing channel if required and decreasing the size of a routing channel if possible by changing the placement of at least one placement row by an amount less than half the height of the placement row. Routing channel size is therefore flexibly adjusted "on-the-fly" during routing, increasing routing efficiency. The adjustment of routing channels in small (5 track) increments is made possible by defining "tall" macros (four transistor rows high) made of "small" (5 track high) transistors.

39 citations


Cited by
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Patent
02 Mar 2001
TL;DR: The STANDARD BLOCK architecture as discussed by the authors provides a new level of abstraction with a granularity and regularity that is most appropriate for the physical implementation of complex, large scale deep-submicron IC designs.
Abstract: A STANDARD BLOCK architecture for integrated circuit (IC) design. The STANDARD BLOCK architecture provides a new level of abstraction with a granularity and regularity that is most appropriate for the physical implementation of complex, large scale deep-submicron IC designs. To this end, the STANDARD BLOCK architecture combines the advantages of standard-cell-based and functional-block-based architectures. The STANDARD BLOCK architecture includes a STANDARD BLOCK form that is physically constrained having one fixed or quantized dimension and one variable dimension that ranges between predefined limits. The STANDARD BLOCK granularity is larger than the standard cell granularity such that each STANDARD BLOCK includes a plurality of standard cells. In the STANDARD BLOCK architecture, each STANDARD BLOCK has flexible physical design properties. In this design style, the STANDARD BLOCKs are provided as general abstractions akin to black boxes whose selected global design aspects are visible to a top-level design tool and whose selected local design aspects are invisible to the top-level design tool. The global design aspects of each STANDARD BLOCK include its fundamental architectural and structural characteristics, including its physically constrained form, and its fundamental power, timing, clock and signal integrity properties. With the STANDARD BLOCK architecture, quantization of the STANDARD BLOCKs' form dimensions relative to IC dimensions can be substantially constant and scalable with increased IC complexity. Thus, STANDARD BLOCK architecture can be applied to any IC designs as well as any intellectual property (IP) designs.

293 citations

Patent
06 Feb 1995
TL;DR: In this article, a device independent, frequency driven layout system and method for field programmable gate arrays (FPGA) is presented, which allows a circuit designer to specify the desired operating frequencies of clock signals in a given design to the automatic layout system to generate, if possible, a physical FPGA layout which will allow the targeted FPGAs device to operate at the specified frequencies.
Abstract: A device independent, frequency driven layout system and method for field programmable gate arrays ("FPGA") which allow for a circuit designer to specify the desired operating frequencies of clock signals in a given design to the automatic layout system to generate, if possible, a physical FPGA layout which will allow the targeted FPGA device to operate at the specified frequencies. Actual net, path and skew requirements are automatically generated and fed to the place and route tools. The system and method of the present invention evaluates the frequency constraints, determines what delay ranges are acceptable for each electrical connection and targets those ranges throughout the layout.

211 citations

Patent
30 Nov 1989
TL;DR: In this article, a system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration, converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture.
Abstract: A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system. A network of internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.

211 citations

Patent
Stephen M. Trimberger1
19 Jul 2004
TL;DR: In this article, the optimal routing line segments and associated buffers are pre-engineered for each family of ASIC chips by simulating wires segments of various lengths using distributed resistance and capacitance wire models, and estimating crosstalk from neighboring line segments.
Abstract: Optimal routing line segments and associated buffers are pre-engineered for each family of ASIC chips by simulating wires segments of various lengths using distributed resistance and capacitance wire models, and by estimating crosstalk from neighboring line segments. During ASIC design, space is reserved on the ASIC substrate for fabricating the buffers, which are selectively connected by local metal and diffusion structures to form long distance interconnections. Signals are passed from an ASIC circuit structure to a selected long distance interconnection by connecting an output terminal of the ASIC structure either to the input terminal of a buffer located at one end of the interconnection, or by connecting the output terminal directed to a line segment of the interconnection.

200 citations

Patent
12 Apr 1996
TL;DR: In this article, the authors present a computer system, method and software product that enables automatic placement and routing of datapath functions using a design methodology that preserves hierarchical and structural regularity in top-down designs for datapaths.
Abstract: A computer system, method and software product enables automatic placement and routing of datapath functions using a design methodology that preserves hiearchical and structural regularity in top down designs for datapaths. The system includes a datapath floorplanner, a datapath placer, and routing space estimator. The datapath floorplanner allows the designer to establish and maintain during floorplannning operations datapath regions that include a number of datapath functions each. The datapath floorplanner creates the datapath regions from a netlist specifying logic cell instances and connectivity information, and from a plurality of tile files. A tile file is a structured description of a datapath function, describing the relative vertical and horizontal placement of all logic cell instances within the datapath function. There is one tile file for each unique datapath function. The datapath function instances then are associated with a particular tile file by the tile file list file. The datapath floorplanner uses the tile files to integrate the placement information with the specific function instances, and further allows the specification of clusters, function interleaving, and net side constraints per region. A datapath placer places the datapath functions in each region using the relative placement information and constraints. The routing space estimator estimates the space needed for routing a placed region. All of this information is interactively provided to the circuit designer so as to allow almost real time modification of datapath placement.

198 citations