Mark Tehranipoor

TL;DR: This article examines the research on hardware Trojans from the last decade and attempts to capture the lessons learned and identifies the most critical lessons for those new to the field and suggests a roadmap for future hardware Trojan research.

TL;DR: This paper presents a comprehensive vulnerability analysis flow at various levels of abstraction of digital-design, that has been utilized to create a suite of Trojans and ‘trust benchmarks’ that can be used by researchers in the community to compare and contrast various Trojan detection techniques.

TL;DR: This survey of RE and anti-RE techniques on the chip, board, and system levels should be of interest to both governmental and industrial bodies whose critical systems and intellectual property (IP) require protection from foreign enemies and counterfeiters who possess advanced RE capabilities.

TL;DR: A novel “bypass attack” is proposed that ensures the locked circuit works even when an incorrect key is applied and makes it possible for an adversary to be oblivious to the type of SAT-resistant protection applied on the circuit, and still be able to restore the circuit to its correct functionality.

TL;DR: A framework named Analyzing Vulnerabilities in FSM (AVFSM) is developed which extracts the state transition graph (including the don't-care states and transitions) from a gate-level netlist using a novel Automatic Test Pattern Generation (ATPG) based approach and quantifies the vulnerabilities of the design to fault injection and hardware Trojan insertion.