Marko Hännikäinen

Bio: Marko Hännikäinen is an academic researcher from Tampere University of Technology. The author has contributed to research in topics: Wireless sensor network & Wireless network. The author has an hindex of 27, co-authored 128 publications receiving 3061 citations.

Advanced prototype platform for a wireless multimedia local area network

Abstract: This paper presents an advanced version of a configurable demonstrator platform developed for a new wireless local area network called TUTWLAN. TUTWLAN is targeted for limited service areas with stationary or portable terminals. Applications range from simple wireless sensors to multimedia laptops. The network supports the different Quality of Service (QoS) requirements of these applications. The improved development platform has been designed because of the restrictions discovered in the first prototype. The new platform provides better testing environment for developing Medium Access Control (MAC) protocols for TUTWLAN and for designing embedded stand-alone applications. Furthermore, various other designs can be tested, for example hardware implementations of encryption algorithms. Both the new and the old prototypes consist of a Digital Signal Processor (DSP), external memory modules for the DSP, and a Field Programmable Gate Array (FPGA) circuit. The platform is connected to a radio module and can be attached to a host computer using Peripheral Component Interconnect (PCI) bus. Compared to the original platform, the new prototype contains more memory, a faster and larger FPGA, and a higher bit-rate radio.

Performance evaluation of UML2-modeled embedded streaming applications with system-level simulation

Abstract: This article presents an efficient method to capture abstract performance model of streaming data real-time embedded systems (RTESs). Unified Modeling Language version 2 (UML2) is used for the performance modeling and as a front-end for a tool framework that enables simulation-based performance evaluation and design-space exploration. The adopted application meta-model in UML resembles the Kahn Process Network (KPN) model and it is targeted at simulation-based performance evaluation. The application workload modeling is done using UML2 activity diagrams, and platform is described with structural UML2 diagrams and model elements. These concepts are defined using a subset of the profile for Modeling and Analysis of Realtime and Embedded (MARTE) systems from OMG and custom stereotype extensions. The goal of the performance modeling and simulation is to achieve early estimates on task response times, processing element, memory, and on-chip network utilizations, among other information that is used for design-space exploration. As a case study, a video codec application on multiple processors is modeled, evaluated, and explored. In comparison to related work, this is the first proposal that defines transformation between UML activity diagrams and streaming data application workload meta models and successfully adopts it for RTES performance evaluation.

Performance Modeling and Reporting for the UML 2.0 Design of Embedded Systems

Abstract: This paper presents a new performance modeling approach for the design of embedded real-time systems using UML 2.0. The approach responds to the lack of specific semantics for the performance modeling. The existing UML metamodel is extended by defining stereotypes to include the message latency and execution time in UML statecharts. The information may contain both the real-time constraints and measured values that are back-annotated to the UML model. Further, fully automated model transformation is used to visualize this information with sequence diagrams. The modeling approach has been prototyped with the UML implementation of a WLAN medium access control protocol. The experiences proved the approach to be practical and intuitive.

Optimal Subset Mapping And Convergence Evaluation of Mapping Algorithms for Distributing Task Graphs on Multiprocessor SoC

Abstract: Mapping an application on multiprocessor system-on-chip (MPSoC) is a crucial step in architecture exploration The problem is to minimize optimization effort and application execution time Applications are modeled as static acyclic task graphs which are mapped to an MPSoC The analysis is based on extensive simulations with 300 node graphs from the standard graph set We present a new algorithm, optimal subset mapping (OSM), that rapidly evaluates task distribution mapping space, and then compare it to simulated annealing (SA) and group migration (GM) algorithms OSM was developed to make architecture exploration faster Efficiency of OSM is 50 times and 24 times than that of GM and SA, respectively, when efficiency is measured as the application speedup divided by the number of iterations needed for optimization This saves 81% and 62% in wall clock optimization time, respectively However, this is a tradeoff because OSM reaches 96% and 89% application speedup compared to GM and SA Results show that OSM and GM have opposite convergence behavior and SA comes between these two

Architecture of a passenger information system for public transport services

Abstract: A passenger information system (PIS) called TUTPIS has been developed for networking passengers with companies that provide public transport services. TUTPIS supports a passenger with personalised, real time information services in all phases of a journey. Services include timetables, travel route searching, route reservations, and electronic payment. TUTPIS is targeted to operate on the developing wireless network infrastructure of mobile, local, and personal networking technologies. A TUTPIS model concentrating on bus services has been implemented using the specification and description language (SDL). The model contains functional implementations of a TUTPIS server and mobile terminals. In addition, the behaviour of external entities, such as buses, trains, and third party systems is implemented for simulations. By simulations, the operability of TUTPIS can be verified and performance estimations for system servers, wireless network throughputs, and mobile terminals derived.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

Survey of Wireless Indoor Positioning Techniques and Systems

Abstract: Wireless indoor positioning systems have become very popular in recent years. These systems have been successfully used in many applications such as asset tracking and inventory management. This paper provides an overview of the existing wireless indoor positioning solutions and attempts to classify different techniques and systems. Three typical location estimation schemes of triangulation, scene analysis, and proximity are analyzed. We also discuss location fingerprinting in detail since it is used in most current system or solutions. We then examine a set of properties by which location systems are evaluated, and apply this evaluation method to survey a number of existing systems. Comprehensive performance comparisons including accuracy, precision, complexity, scalability, robustness, and cost are presented.

The LED block cipher

Abstract: We present a new block cipher LED. While dedicated to compact hardware implementation, and offering the smallest silicon footprint among comparable block ciphers, the cipher has been designed to simultaneously tackle three additional goals. First, we explore the role of an ultra-light (in fact non-existent) key schedule. Second, we consider the resistance of ciphers, and LED in particular, to related-key attacks: we are able to derive simple yet interesting AES-like security proofs for LED regarding related- or single-key attacks. And third, while we provide a block cipher that is very compact in hardware, we aim to maintain a reasonable performance profile for software implementation.

KATAN and KTANTAN -- A Family of Small and Efficient Hardware-Oriented Block Ciphers

Abstract: In this paper we propose a new family of very efficient hardware oriented block ciphers. The family contains six block ciphers divided into two flavors. All block ciphers share the 80-bit key size and security level. The first flavor, KATAN, is composed of three block ciphers, with 32, 48, or 64-bit block size. The second flavor, KTANTAN, contains the other three ciphers with the same block sizes, and is more compact in hardware, as the key is burnt into the device (and cannot be changed). The smallest cipher of the entire family, KTANTAN32, can be implemented in 462 GE while achieving encryption speed of 12.5 KBit/sec (at 100 KHz). KTANTAN48, which is the version we recommend for RFID tags uses 588 GE, whereas KATAN64, the largest and most flexible candidate of the family, uses 1054 GE and has a throughput of 25.1 Kbit/sec (at 100 KHz).