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Marko Hännikäinen

Bio: Marko Hännikäinen is an academic researcher from Tampere University of Technology. The author has contributed to research in topics: Wireless sensor network & Wireless network. The author has an hindex of 27, co-authored 128 publications receiving 3061 citations.


Papers
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Proceedings ArticleDOI
18 Apr 2006
TL;DR: The shared instruction memory is shown to be area-efficient and sufficient in performance for configurations up to five processors, as the drop in encoded video frame rate stays below one compared to distributed instruction memory organization.
Abstract: The impact of shared instruction memory on performance is measured and analyzed for an FPGA-based multiprocessor system-on-chip (MP-SoC) with an MPEG-4 video encoding application. Our MP-SoC architecture allows arbitrary scaling of the number of synthesized processors and includes a monitoring unit for memory transfers. Based on the measurements with up to four processors on Altera Stratix 1S40, an estimate of the effect of the shared memory for larger configurations is presented. The shared instruction memory is shown to be area-efficient and sufficient in performance for configurations up to five processors, as the drop in encoded video frame rate stays below one compared to distributed instruction memory organization

5 citations

Proceedings ArticleDOI
TL;DR: A novel scheme of dynamic power management for UML modeled applications that are executed on a multiprocessor System-on-Chip (SoC) in a distributed manner that integrates the well-known power management techniques tightly with the UML based design of embedded systems in a novel way.
Abstract: The paper presents a novel scheme of dynamic power management for UML modeled applications that are executed on a multiprocessor System-on-Chip (SoC) in a distributed manner. The UML models for both application and architecture are designed according to a well-defined UML profile for embedded system design, called TUT-Profile. Application processes are considered as elementary units of distributed execution, and their mapping on a multiprocessor SoC can be dynamically changed at run-time. Our approach on the dynamic power management balances utilized processor resources against current workload at runtime by (1) observing the processor and workload statistics, (2) re-evaluating the amount of required resources (i.e. the number of active processors), and (3) re-mapping the application processes to the minimum set of active processors. The inactive processors are set to a power-save state by using clock-gating. The approach integrates the well-known power management techniques tightly with the UML based design of embedded systems in a novel way. We evaluated the dynamic power management with a WLAN terminal implemented on a multiprocessor SoC on Altera Stratix II FPGA containing up to five Nios II processors and dedicated hardware accelerators. Measurements proved up to 21% savings in the power consumption of the whole FPGA board.

5 citations

Proceedings ArticleDOI
07 Aug 2002
TL;DR: The architecture of a wireless video transfer demonstrator, which contains modules for video capture, encoding, stream protection and transfer for wireless link or network, as well as for decoding and displaying at the receiver, is presented.
Abstract: This paper presents the architecture of a wireless video transfer demonstrator. The demonstrator has been implemented for developing control protocols and QoS support for real-time video streaming services. The demonstrator contains modules for video capture, encoding, stream protection and transfer for wireless link or network, as well as for decoding and displaying at the receiver. H.263 encoding is performed in real-time using dedicated hardware. A video control protocol has been designed and implemented for managing the stream transfer and for collecting measurement information. The current implementation operates over wireless LAN, GSM data, Bluetooth and a proprietary wireless LAN called TUTWLAN. In addition, a special module has been implemented for simulating different wireless links or networks locally.

5 citations

Journal ArticleDOI
01 Oct 2006
TL;DR: This paper shows how a bus topology performs as a System-on-Chip (SoC) interconnection with an MPEG-4 video encoding application on FPGA, and it is shown that HIBI is not the limiting factor.
Abstract: Some previous theoretical studies imply that mesh and other topologies outperform bus as a System-on-Chip (SoC) interconnection. This paper shows how bus performs in a real implementation. We measure and analyze Heterogeneous IP Block Interconnection (HIBI) bus for a multiple clock domain, Multiprocessor System-on-Chip (MPSoC) with an MPEG-4 video encoding application on FPGA. The system is benchmarked with seven different bus clock frequencies and four buffer sizes. A custom hardware monitor is used for the measurements. It is shown that the bus performance is adequate with significantly lower clock frequencies (5 MHz) than other components of the MPSoC (50-100 MHz). Based on the measurements, an estimate for the required bus and CPU frequencies for larger image formats and increased frames/s is shown. In contrast to the theoretical studies, the estimate shows that the bus is still a strong candidate for the SoC interconnection, because it is not the performance-limiting factor.

5 citations

Proceedings ArticleDOI
30 Aug 2006
TL;DR: This paper compares the SoC GALS architectures to a synchronous architecture with a fully functional MPEG-4 video encoder on FPGA, showing that the area and performance overhead of GALS is only 1%.
Abstract: In large System-on-Chip (SoC) architectures, balancing the clock network is increasingly difficult. Globally Asynchronous Locally Synchronous (GALS) removes the need for global clock net, and also provides efficient means for managing the complexity and re-use in large architectures. However, quantitative comparisons of GALS against similar synchronous structures are rare for full SoC architectures. In this paper, we compare our SoC GALS architectures to a synchronous architecture with a fully functional MPEG-4 video encoder on FPGA. The results show that the area and performance overhead of GALS is only 1%. That is negligible compared to the benefits of the GALS architecture such as multiple clock frequencies for Intellectual Property (IP) blocks and dynamic frequency/voltage scaling, clock tree removal, and re-usability. Our architecture does not require modifications to the IP blocks already used with synchronous architectures, providing an ideal solution for rapid switch to GALS architecture.

5 citations


Cited by
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Journal ArticleDOI

[...]

08 Dec 2001-BMJ
TL;DR: There is, I think, something ethereal about i —the square root of minus one, which seems an odd beast at that time—an intruder hovering on the edge of reality.
Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

33,785 citations

Journal ArticleDOI
01 Nov 2007
TL;DR: Comprehensive performance comparisons including accuracy, precision, complexity, scalability, robustness, and cost are presented.
Abstract: Wireless indoor positioning systems have become very popular in recent years. These systems have been successfully used in many applications such as asset tracking and inventory management. This paper provides an overview of the existing wireless indoor positioning solutions and attempts to classify different techniques and systems. Three typical location estimation schemes of triangulation, scene analysis, and proximity are analyzed. We also discuss location fingerprinting in detail since it is used in most current system or solutions. We then examine a set of properties by which location systems are evaluated, and apply this evaluation method to survey a number of existing systems. Comprehensive performance comparisons including accuracy, precision, complexity, scalability, robustness, and cost are presented.

4,123 citations

Book ChapterDOI
28 Sep 2011
TL;DR: This work considers the resistance of ciphers, and LED in particular, to related-key attacks, and is able to derive simple yet interesting AES-like security proofs for LED regarding related- or single- key attacks.
Abstract: We present a new block cipher LED. While dedicated to compact hardware implementation, and offering the smallest silicon footprint among comparable block ciphers, the cipher has been designed to simultaneously tackle three additional goals. First, we explore the role of an ultra-light (in fact non-existent) key schedule. Second, we consider the resistance of ciphers, and LED in particular, to related-key attacks: we are able to derive simple yet interesting AES-like security proofs for LED regarding related- or single-key attacks. And third, while we provide a block cipher that is very compact in hardware, we aim to maintain a reasonable performance profile for software implementation.

848 citations

Book ChapterDOI
30 Aug 2009
TL;DR: A new family of very efficient hardware oriented block ciphers divided into two flavors, which is more compact in hardware, as the key is burnt into the device (and cannot be changed), and achieves encryption speed of 12.5 KBit/sec.
Abstract: In this paper we propose a new family of very efficient hardware oriented block ciphers. The family contains six block ciphers divided into two flavors. All block ciphers share the 80-bit key size and security level. The first flavor, KATAN, is composed of three block ciphers, with 32, 48, or 64-bit block size. The second flavor, KTANTAN, contains the other three ciphers with the same block sizes, and is more compact in hardware, as the key is burnt into the device (and cannot be changed). The smallest cipher of the entire family, KTANTAN32, can be implemented in 462 GE while achieving encryption speed of 12.5 KBit/sec (at 100 KHz). KTANTAN48, which is the version we recommend for RFID tags uses 588 GE, whereas KATAN64, the largest and most flexible candidate of the family, uses 1054 GE and has a throughput of 25.1 Kbit/sec (at 100 KHz).

733 citations