Sparse Superposition Codes are a class of capacity achieving codes for which decoding can be interpreted as a compressive sensing problem. The approximate message passing algorithm, proven to be effective in compressive sensing, has been proposed in different incarnations as a valid decoding approach. However, most literature focuses on infinite code length and asymptotic performance, while the strong reliance on matrix-and vector-wise operations suggests that a hardware-oriented approach might be more efficient. This work analyzes the performance of two decoding algorithms with finite code lengths and fixed point precision: 5-bit codeword symbol quantization is shown to cause performance degradation ≤ 0.15 dB. In-algorithm quantization values are proposed, together with code construction and algorithm approximations that cause negligible performance degradation. After selecting a set of codes as a case study, a decoding complexity estimation is performed, demonstrating that a fully parallel architecture is unfeasible. Suggestions and improvements towards partially-parallel solutions are given.

Sparse superposition codes: A practical approach

Using more processors for parallel turbo decoding is an important issue to speed up the processing at the receiver of a communication system. Butterfly networks used to map the addresses of extrinsic values represent an elegant and simple solution in parallel turbo decoding. Recently, it has been shown that quadratic permutation polynomial (QPP) interleavers allow an easy way to compute the control bits for a butterfly network. In this paper we show that not only QPP interleavers, but any degree permutation polynomial (PP) interleavers and almost regular permutation (ARP) interleavers also allow the same easy way to compute the control bits required in butterfly networks. As a consequence, it is useful to apply the butterfly networks in parallel turbo decoding when using these performant algebraic interleavers.

Parallel access by butterfly networks for any degree permutation polynomial and ARP interleavers

Parallel interleaver is an indispensable component for the parallel turbo decoder. The ever increasing data rates motivated by throughput-intensive applications result in higher parallelism of turbo decoder design, rendering the efficient realization of the interleaver a highly challenging work. This paper addresses the design of quadratic permutation polynomial (QPP) interleaver for the symbol-based serial MAP (SMAP) and the cross MAP (XMAP) parallel decoding. To circumvent the access conflicts incurred by the randomness of the interleaving function, the stratssonably position soft outputs of maximum a-posteriori (MAP) decoders in memory instances is firstly investigated. On this basis, a hardware-friendly parallel interleaver architecture is proposed by utilizing the algebraic properties of QPP function. Theoretical evaluation and experimental results demonstrate that the proposed design gains boosted hardware efficiency compared to existing schemes, and is applicable to both SMAP and XMAP decoding with arbitrary parallelism.

Design of QPP Interleavers for the Parallel Turbo Decoding Architecture

Datapath widths in state-of-the-art Turbo and Viterbi decoder implementations depend on estimated upper bounds of the differences of processed metrics. Aiming at highest area and energy efficiency, this paper presents guidelines for designing Turbo and Viterbi decoder datapaths with minimal widths. This is based on maximum absolute values of branch, state and path metric differences within theMax-Log-MAP respectively Viterbi decoding algorithm applying modulo normalization. The proposed methodology for determining the maximum absolute values covers punctured as well as n-input binary convolutional and Turbo codes so it accommodates higherradix add-compare-select operations. Maximum absolute values of metric differences and minimum datapath widths are presented for the 3GPP-LTE, DVB-RCS2 and IEEE-802.16 (WiMAX) compliant Turbo decoders and for the IEEE-802.11 (Wi-Fi), IEEE-802.16 (WiMAX) and 3GPP-LTE compliant Viterbi decoders. Besides, a new dynamic branch-metric saturation scheme is presented, which enables a further datapath width reduction within Turbo decoders. In total, a datapath width reduction of two bits (?20 %) is achieved applying radix-4 Max-Log-MAP arithmetic. An overall area-time-energy complexity reduction of 31% is achieved for a soft-input soft-output decoder and of 24% for the LTE Turbo decoder.

Optimal Datapath Widths Within Turbo and Viterbi Decoders for High Area- and Energy-Efficiency

The Long Term Evolution (LTE) networks main objective is to support the next generation wireless communication systems. But most of the LTE approaches are suffer from decoding latency. Hence results in drop of data rate and this is not supported by the 4G LTE standards. To overcome this few parallel architectures has been introduced with the cost of power and silicon chip area. One promising decoding algorithm to overcome the decoding latency is Maximum a Posteriori (MAP) algorithm. The MAP has two computationally challenging α and β units. These two units have critical path and are to be reduced. A novel architecture for Add-Compare-Select (ACS) is proposed with clock gating techniques to reduce the unnecessary power dissipation across the recursive computational units. The proposed technique is applied with max-log MAP algorithm to precise the approximation. The overall design in implemented in a 45nm CMOS technology and results in 179.2mW of power dissipation which results in 34.6% less power compared to reported design while monitoring the moderate or same throughput level.

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Energy Efficient VLSI Architecture for Variable Iterative 4G LTE Turbo Decoder

Quadratic-permutation-polynomial (QPP) interleavers are utilized in Turbo coding of the 4G-mobile-system LTE-Advanced due to the support of parallel, contention-free memory accesses. In principle, throughput rates of 1 Gbit/s can be supported with such interleavers in today's CMOS technologies. A systematic examination of the QPP interleaver properties has led to several design improvements concerning silicon area, energy per operation and the support of highly parallelized Turbo decoders. Regarding the interleaver network, it is proven that hardware-efficient butterfly and Bene?s networks can be applied with negligible configuration overhead. With respect to the interleaver address generation, we propose and analyze a recursive address calculation method.

Efficient VLSI architectures of QPP interleavers for LTE turbo decoders

Data path widths in state-of-the-art Turbo decoder implementations depend on estimates for the upper bounds of the dynamic ranges of processed metrics. Aiming at highest area and energy efficiency, this paper presents guidelines for designing SISO and Turbo decoder data paths with minimal widths. This is based on least upper bounds for the dynamic ranges of internal metrics within the underlying Max-Log-MAP algorithm. Least upper bounds are presented for the LTE Turbo decoder. Furthermore, a new dynamic branch metric saturation scheme is presented in order to optimize the hardware utilization by proper adjusting the correlated upper state and branch metric bounds. In total, a data path width reduction of two bits is achieved applying radix-4 Max-Log-MAP arithmetic. An overall area-energy complexity reduction of 33% is achieved for the SISO decoder and of 28% for the LTE Turbo decoder.

Martin Broich

Papers

Efficient VLSI architectures of QPP interleavers for LTE turbo decoders

Optimal data path widths for energy- and area-efficient Max-Log-MAP based LTE Turbo decoders

Optimal Datapath Widths Within Turbo and Viterbi Decoders for High Area- and Energy-Efficiency