Martin von Haartman

Bio: Martin von Haartman is an academic researcher. The author has contributed to research in topics: Electronic circuit & CMOS. The author has an hindex of 1, co-authored 1 publications receiving 20 citations.

Low-frequency noise characterization, evaluation and modeling of advanced Si- and SiGe-based CMOS transistors

Abstract: A wide variety of novel complementary-metal-oxide-semiconductor (CMOS) devices that are strong contenders for future high-speed and low-noise RF circuits have been evaluated by means of static elec ...

1/f Noise Sources

Abstract: This survey deals with 1/f noise in homogeneous semiconductor samples. A distinction is made between mobility noise and number noise. It is shown that there always is mobility noise with an /spl alpha/ value with a magnitude in the order of 10/sup -4/. Damaging the crystal has a strong influence on /spl alpha/, /spl alpha/ may increase by orders of magnitude. Some theoretical models are briefly discussed none of them can explain all experimental results. The /spl alpha/ values of several semiconductors are given. These values can be used in calculations of 1/f noise in devices. >

Design of CMOS analog integrated circuits as readout electronics for High-TC superconductor and semiconductor terahertz bolometric sensors

Abstract: This PhD thesis deals with the design of a CMOS integrated circuit as a readout electronic for the THz bolometric detectors, either semiconductor or high-Tc superconductor. We study a chain of the analog signal processing composed of the differential fixed-gain amplifier for the temperature range of 40 to 400K, as well as of the high dynamic range low-pass active frequency filter. As the optimal amplifier configuration, a feedback-free architecture was selected in order to reach high frequency bandwidth (17MHz for gain 40dB), low quiescent current (Iq=2mA) and high input impedance. In this amplifier, the gain is set in the CMOS structure via two different methods and the accuracy is verified by wide-temperature measurements of the fabricated integrated circuit. Consequently, the behaviour of the frequency filters is examined namely in the stopband, aiming to increase the maximal cut-off frequency. As an outcome, two structures with low influence of real active elements' parameters are designed: improved type-II Sallen-Key and the structure based on the CCII- current conveyor. In the last part, the integrated CCII- with very low output impedance is presented.

Delocalized photonic deep learning on the internet’s edge

Abstract: Advanced machine learning models are currently impossible to run on edge devices such as smart sensors and unmanned aerial vehicles owing to constraints on power, processing, and memory. We introduce an approach to machine learning inference based on delocalized analog processing across networks. In this approach, named Netcast, cloud-based “smart transceivers” stream weight data to edge devices, enabling ultraefficient photonic inference. We demonstrate image recognition at ultralow optical energy of 40 attojoules per multiply (<1 photon per multiply) at 98.8% (93%) classification accuracy. We reproduce this performance in a Boston-area field trial over 86 kilometers of deployed optical fiber, wavelength multiplexed over 3 terahertz of optical bandwidth. Netcast allows milliwatt-class edge devices with minimal memory and processing to compute at teraFLOPS rates reserved for high-power (>100 watts) cloud computers. Description Learning on the edge Smart devices such as cell phones and sensors are low-power electronics operating on the edge of the internet. Although they are increasingly more powerful, they cannot perform complex machine learning tasks locally. Instead, such devices offload these tasks to the cloud, where they are performed by factory-sized servers in data centers, creating issues related to large power consumption, latency, and data privacy. Sludds et al. introduce an edge-computing architecture called NetCast that makes use of the strengths of photonics and electronics. In this method, smart transceivers periodically broadcast the weights of commonly used deep neural networks. The architecture allows low-power edge devices with minimal memory and processing to compute at teraflop rates otherwise reserved for high-power cloud computers. —ISO A new computing architecture allows low-power edge devices to perform at levels otherwise reserved for data centers.

Metrology for the Electrical Characterization of Semiconductor Nanowires

Abstract: Nanoelectronic devices based upon self-assembled semiconductor nanowires are excellent research tools for investigating the behavior of structures with sublithographic features as well as a promising basis for future information processing technologies. New test structures and associated electrical measurement methods are the primary metrology needs necessary to enable the development, assessment, and adoption of emerging nanowire electronics. We describe two unique approaches to successfully fabricate nanowire devices: one based upon harvesting and positioning nanowires and one based upon the direct growth of nanowires in predefined locations. Test structures are fabricated and electronically characterized to probe the fundamental properties of chemical-vapor-deposition-grown silicon nanowires. Important information about current transport and fluctuations in materials and devices can be derived from noise measurements, and low-frequency $ \hbox{1}/f$ noise has traditionally been utilized as a quality and reliability indicator for semiconductor devices. Both low-frequency $\hbox{1}/f$ noise and random telegraph signals are shown here to be powerful methods for probing trapping defects in nanoelectronic devices.

Characterization and Modeling of Flicker Noise in FinFETs at Advanced Technology Node

Abstract: 1/ ${f}$ noise is characterized on thick and thin-gate oxide-based FinFETs for different channel lengths. The devices exhibit gate bias dependence in 1/ ${f}$ noise even in the weak-inversion region of operation which cannot be explained by the existing flicker noise model. We attribute this phenomenon to the non-uniform oxide-trap distribution in energy or space. Based on our characterization results for n- and p-channel FinFETs, we have improved the BSIM-CMG industry standard compact model for the FinFETs. The improved model is able to capture the 1/ ${f}$ noise behavior over a wide range of biases, channel lengths, fin numbers, and number of fingers.