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Author

Masaaki Kawai

Other affiliations: Nippon Telegraph and Telephone
Bio: Masaaki Kawai is an academic researcher from Fujitsu. The author has contributed to research in topics: Clock signal & Signal. The author has an hindex of 9, co-authored 38 publications receiving 349 citations. Previous affiliations of Masaaki Kawai include Nippon Telegraph and Telephone.

Papers
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Patent
30 Apr 1992
TL;DR: In this paper, the authors proposed a system for monitoring an ATM cross-connecting apparatus by inputting a test cell through a path for a main signal into the ATM cross connecting apparatus, and examining the cell after the cell passed through the ATMs.
Abstract: A system for monitoring an ATM cross-connecting apparatus by inputting a test cell through a path for a main signal into the ATM cross-connecting apparatus, and examining the cell after the cell passed through the ATM cross-connecting apparatus. An initial value of a PN sequence and the PN sequence generated based on the initial bit sequence is written in the test cell before inputting to the ATM cross-connecting apparatus. When examining the test cell, the initial bit sequence and the PN sequence are read from the cell, a PN sequence is generated based on the initial bit sequence, and is then compared with the PN sequence read from the test cell to detect an error in the test cell. In addition, a bit pattern indicating a primitive polynomial to generate the PN sequence may be written in the test cell. In this case, the bit pattern is used for generating the PN sequence when examining the test cell. Further, the same VPI values may be written in both the header and the information field of the test cell before inputting the cell to the ATM cross-connecting apparatus, and the VPI value in the information field is compared with a VPI value in the header of the test cell when examining the test cell.

74 citations

Patent
28 May 1992
TL;DR: In this article, a cross-connection apparatus for B-ISDN includes plural interface units, multiplexers, virtual path identifier (VPI) conversion tables, demultiplexers and loop-back units and a switch unit.
Abstract: A cross-connection apparatus for B-ISDN includes plural interface units, multiplexers, virtual path identifier (VPI) conversion tables, demultiplexers, and loop-back units and a switch unit The interface unit has a reception port for receiving an ATM cell or inserting a monitor cell, and a transmission port for transferring the ATM cell or extracting the monitor cell; The multiplexer is operatively connected to corresponding interface unit for multiplexing the monitor cell; The VPI conversion tables is operatively connected to corresponding multiplexer for converting the VPI to change a transmission route of the monitor cell; The switch unit is operatively connected to the VPI conversion tables for switching the transmission route of the monitor cell based on the VPI; The demultiplexer is operatively connected to the switch unit for demultiplexing the monitor cell and transferring the monitor cell to the transmission port; The loop-back unit is operatively connected to corresponding interface unit for changing the transmission route so as to transfer the monitor cell to the same interface unit which the monitor cell is inserted, and as a result, the apparatus can be monitored by comparing the inserted monitor cell with the extracted monitor cell in the same interface unit

54 citations

Patent
08 Mar 1995
TL;DR: In this paper, a line interface is provided for performing a switching process of a fixed length cell consisting of data and a cell header, where individual units are individually connected to the plurality of lines accommodated therein and individually process the cells.
Abstract: Switching equipment in provided for performing a switching process of a fixed length cell consisting of data and a cell header. A line interface provided in the switching equipment accommodates a plurality of lines and, at the same time, processes the data from each line on a cell unit. The line interface includes individual units and a common unit. The individual units are individually connected to the plurality of lines accommodated therein and individually process the cells. The common unit is connected to the individual units and, at the same time, effects batch-processing of the cells processed by the individual units.

52 citations

Patent
06 Nov 1995
TL;DR: In this article, a switching equipment accommodates lines and includes a line interface for processing data from the line on the unit of cell, where the line interface has a basic processing unit and an additional processing unit.
Abstract: A switching equipment accommodates lines and includes a line interface for processing data from the line on the unit of cell. The line interface has a basic processing unit and an additional processing unit. The basic processing unit performs a basic process on the cell. The additional processing unit separated from the basic processing unit but disconnectably connected to the basic processing unit executes an additional process on the cell. The additional processing unit includes a plurality of processing blocks for effecting a plurality of additional processes on the cells. Each processing block is individually disconnectably connected to the basic processing unit. The basic processing unit includes a selecting portion for selecting, when one or more processing blocks within the additional processing unit are connected, the connected processing blocks and performing the additional process on the cell.

17 citations

Patent
22 Feb 1989
TL;DR: In this article, a circuit for generating a discrimination voltage level V ref which is used as a reference voltage to discriminate between two adjacent logic levels or an input signal which can have a plurality of different voltage levels generally corresponding to different logic levels is presented.
Abstract: A circuit for generating a discrimination voltage level V ref which is used as a reference voltage to discriminate between two adjacent logic levels or an input signal which can have a plurality of different voltage levels generally corresponding to a plurality of respective, different logic levels. The frequency at which the levels of the input signals lie in the upper half of the vicinity (i.e., the voltage range from the level V ref -ΔV to the level V ref +ΔV) of the discrimination voltage level (i.e., the "upper half" thereof being the voltage range from V ref to V ref +ΔV, "ΔV" being a predetermined off-set value) and the frequency at which the levels of the input signals lie in the lower half of the vicinity (i.e., as above defined) of the discrimination level (i.e., the "low half" thereof being the voltage range from V ref -ΔV to V ref ) are compared, and the discrimination level is controlled so that the above two frequencies are the same.

17 citations


Cited by
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Patent
06 Nov 1998
TL;DR: In this paper, a data transmission system includes probes (probe A, probe B) connected between end user sites (site A, site B) and a data switching network (12).
Abstract: A data transmission system includes probes (probe A, probe B) connected between end user sites (site A, site B) and a data switching network (12). Each probe is connected to the switching network (12) via an access channel (20, 21, 26 or 27) wherein transmission circuits establish paths between the sites through the access channel (20, 21, 26 or 27) and switching network (12). The probes capture and retransmit data traveling between the sites over respective transmission circuits, and can thereby insert service level anaylsis (SLA) messages into data traffic in order to actively communicate network performance information to other probes. For each transmission circuit, the probes periodically collect measurements related to one or more network performance metrics, including round-trip delay (RTD), data delivery ratio (DDR) and network availability. During each SLA measurement cycle, a sequence of SLA messages is exchanged over each transmission circuit, which messages contain data used to determine RTD and DDR.

218 citations

Patent
18 Jul 1996
TL;DR: In this paper, an ATM network switch and method of utilization for adaptively providing integrated services therein is disclosed, in which the allocated bandwidth for one connection has been consumed, or if the connection is not entitled to allocated bandwidth, the connection can use dynamic bandwidth arbitration, or a combination of both allocated and dynamic.
Abstract: An ATM network switch and method of utilization for adaptively providing integrated services therein is disclosed. In providing such integrated services, if the allocated bandwidth for one connection has been consumed, or if the connection is not entitled to allocated bandwidth, the connection can optionally use dynamic bandwidth arbitration, or a combination of both allocated and dynamic. The switch includes an input port processor, a bandwidth arbiter, and an output port processor. Cells are transmitted from the input to the output, under the control of respective port processors and the bandwidth arbiter. Flow control is implemented on a per-connection basis. Individual queues are then assigned to traffic type groups in order to provide traffic type flow control. Based upon prioritization information associated with the cell at the input, cells are prioritized and transmitted from the output, with each cell maintained in the same order, relative to other cells on a connection, in which it was received.

212 citations

Patent
22 Dec 2003
TL;DR: In this article, a constant current circuit unit includes one resistor and two transistors mounted on a surface of a sub-substrate on which a conductive land is formed, which is bonded to a main substrate.
Abstract: In a module socket, a connecter and a connector are connected by wiring, and three LED modules are connected in parallel with respect to a constant voltage circuit unit via the wiring. Each module has a constant current circuit unit and an LED mounting unit. The constant current circuit unit includes one resistor and two transistors mounted on a surface of a sub-substrate on which a conductive land is formed. The sub-substrate is bonded to a main substrate.

171 citations

Patent
Motoshi Ito1, Takashi Ishida1, Hiroshi Ueda1, Yoshikazu Yamamoto1, Mamoru Shoji1 
08 Jan 2003
TL;DR: In this paper, a multi-layered information recording medium including a plurality of recording layers is considered, where a first spare area of the plurality of spare areas is positioned so as to be contiguous to a first user data area of a first recording layer.
Abstract: A multi-layered information recording medium including a plurality of recording layers, the multi-layered information recording medium comprising: a user data area for recording user data; and a plurality of spare areas including at least one replacement region, wherein when the user data area includes at least one defect region, the at least one replacement region may be used in place of the at least one defect region, wherein a first spare area of the plurality of spare areas is positioned so as to be contiguous to a first user data area of a first recording layer, a second spare area of the plurality of spare areas is positioned so as to be contiguous to a second user data area of a second recording layer, and the first spare area and the second spare area are positioned approximately at the same radial position on the multi-layered information recording medium.

140 citations

Patent
18 Jul 1996
TL;DR: In this paper, an asynchronous transfer mode (ATM) based service consolidation switch (10) includes an input/output module (22) having a TSPP processor (90) and a from-switch port processor (FSPP) (92) communicating with a bandwidth arbiter (114), multipoint topology controllers (116), and a data crossbar (117) on a switch control module (32).
Abstract: An asynchronous transfer mode (ATM) based service consolidation switch (10) includes an input/output module (22) having a to-switch port (TSPP) processor (90) and a from-switch port processor (FSPP) (92). The TSPP (90) and the FSPP (92) communicate with a bandwidth arbiter (114), multipoint topology controllers (116), and a data crossbar (117) on a switch control module (32). The TSPP (90) receives traffic over links for conversion into an internal cell format. Internal cells are buffered until allowed to transfer to an appropriate FSPP (92). Multipoint topology controllers (116) performs translations for internal switch flow control through interactions between the TSPPs (90), FSPPs (92), and the bandwidth arbiter (114). The bandwidth arbiter (114) performs appropriate bandwidth arbitration to allow internal cells to flow from TSPPs (90) to FSPPs (92) over the data crossbar (117).

138 citations