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Masahiko Motoyama

Bio: Masahiko Motoyama is an academic researcher from Toshiba. The author has contributed to research in topics: Encryption & Asynchronous Transfer Mode. The author has an hindex of 10, co-authored 24 publications receiving 457 citations.

Papers
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Book ChapterDOI
14 May 2001
TL;DR: An implementation of RSA cryptosystem using the RNS Montgomery multiplication is described, and an implementation method using the Chinese Remainder Theorem (CRT) is presented.
Abstract: We proposed a fast parallel algorithm of Montgomery multiplication based on Residue Number Systems (RNS). An implementation of RSA cryptosystem using the RNS Montgomery multiplication is described in this paper. We discuss how to choose the base size of RNS and the number of parallel processing units. An implementation method using the Chinese Remainder Theorem (CRT) is also presented. An LSI prototype adopting the proposed Cox-Rower Architecture achieves 1024- bit RSA transactions in 4.2 msec without CRT and 2.4 msec with CRT, when the operating frequency is 80 MHz and the total number of logic gates is 333 KG for 11 parallel processing units.

128 citations

Journal ArticleDOI
TL;DR: Speedup, flow control, and input slot rotation functions are provided in order to interconnect LSIs for scaling-up without degrading cell loss rates and can make the cell loss- rate for a Clos three-stage network superior to that for the output buffer switch which includes the same amount of buffer space.
Abstract: The authors present a one-chip scalable 8*8 shared buffer switch LSI which includes a 256-cell buffer. Speedup, flow control, and input slot rotation functions are provided in order to interconnect LSIs for scaling-up without degrading cell loss rates. Computer simulations show that these functions bring a satisfactory result and can make the cell loss- rate for a Clos three-stage network superior to that for the output buffer switch which includes the same amount of buffer space. A 0.8 mu m BiCMOS process is employed for this LSI. The total number of transistors is one million. This LSI has already been fabricated. >

75 citations

Patent
11 Jul 2001
TL;DR: Expanded key schedule circuit for common key encryption system in which expanded keys are used in a predetermined order in data randomizing process for encryption and in a reversed order for decryption, comprises round processing circuits connected in series as discussed by the authors.
Abstract: Expanded key schedule circuit for common key encryption system in which expanded keys are used in a predetermined order in data randomizing process for encryption and in a reversed order in data randomizing process for decryption, comprises round processing circuits connected in series. The round processing circuits subject the common key or sub key of a previous stage to a round function to output a sub key. The sub key of the last stage is equal to the common key. The expanded keys are generated from the sub keys.

42 citations

Proceedings ArticleDOI
01 Feb 1996
TL;DR: The switch element (SE) is a 622Mb/s, 8/spl times/8 shared-buffer ATM switch LSI for backbone LAN and WAN applications, supporting 5 QoS classes delay priority and link-by-link multicast.
Abstract: The switch element (SE) is a 622Mb/s, 8/spl times/8 shared-buffer ATM switch LSI for backbone LAN and WAN applications. The SE has 5 Gbps bandwidth, supporting 5 QoS classes delay priority and link-by-link multicast. Up to a 32/spl times/32 switch with 20 Gbps bandwidth can be configured using multiple SEs and distributor/arbiter (DA) LSIs.

36 citations

Patent
08 Oct 1991
TL;DR: A unit cell switch includes a plurality of input communication routes and output communication routes for transferring data cells there between, the plurality of first conversion devices for converting each cell given from these input communications routes into a desired form, and the second conversion devices to convert each data given from the first converting devices into a suitable form and transferring the resultant data to one of these output communications routes as mentioned in this paper, and a control device holds and controls route and address information on cells to be stored in the cell storing devices as unitary data.
Abstract: A unit cell switch includes a plurality of input communication routes and output communication routes for transferring data cells therebetween, a plurality of first conversion devices for converting each cell given from these input communication routes into a desired form, a plurality of second conversion devices for converting each data given from the first conversion devices into a suitable form and transferring the resultant data to one of these output communication routes Cell storing devices respectively receive and temporarily store cells transferred from corresponding first conversion devices based on address information given to the cells A control device holds and controls route and address information on cells to be stored in the cell storing devices as unitary data, and decides a write address of each cell storing device to which a cell is given from the corresponding first cell conversion device and a read address of each cell storing device from which a cell is outputted to a cell switch device based on the route and address information A cell switch device introduces cells to desired second cell conversion devices from corresponding cell storing devices under control of the transfer control device

33 citations


Cited by
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Patent
Noboru Shibata1, Tomoharu Tanaka1
09 Mar 2007
TL;DR: In this paper, a memory cell array has a first and a second storage area, the first storage area has a memory elements selected by an address signal, and the second storage is a control circuit with a fuse element.
Abstract: A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

385 citations

Journal ArticleDOI
TL;DR: This work presents the first implementation of RSA in the residue number system (RNS) which does not require any conversion, either from radix to RNS beforehand or RNS to radix afterward, based on an optimized RNS version of Montgomery multiplication.
Abstract: We present the first implementation of RSA in the residue number system (RNS) which does not require any conversion, either from radix to RNS beforehand or RNS to radix afterward. Our solution is based on an optimized RNS version of Montgomery multiplication. Thanks to the RNS, the proposed algorithms are highly parallelizable and seem then well suited to hardware implementations. We give the computational procedure both parties must follow in order to recover the correct result at the end of the transaction (encryption or signature).

258 citations

Patent
21 May 2004
TL;DR: In this paper, a data storage and retrieval device and method is described, which includes at least one magnetic storage medium configured to store target data and at least a re-configurable logic device comprising an FPGA coupled to the at least 1 magnetic medium and configured to read a continuous stream of target data therefrom, having been configured with a template or as desired to fit the type of search and data being searched.
Abstract: A data storage and retrieval device and method is disclosed. The device includes at least one magnetic storage medium configured to store target data and at least one re-configurable logic device comprising an FPGA coupled to the at least one magnetic storage medium and configured to read a continuous stream of target data therefrom, having been configured with a template or as otherwise desired to fit the type of search and data being searched. The re-configurable logic device is configured to receive at least one search inquiry in the form of a data key and to determine a match between the data key and the target data as it is being read from the at least one magnetic storage medium. This device and method can perform a variety of searches on the target data including without limitation exact and approximate match searches, sequence match searches, image match searches and data reduction searches. This device and method may be provided as part of a stand-alone computer system, embodied in a network attached storage device, or can otherwise be provided as part of a computer LAN or WAN. In addition to performing search and data reduction operations, this device may also be used to perform a variety of other processing operations including encryption, decryption, compression, decompression, and combinations thereof.

255 citations

Journal ArticleDOI
TL;DR: The design and the implementation of input/output (I/O) interface circuits for Gb/s-per-pin operation, fully compatible with low-voltage differential signaling (LVDS) standard are presented.
Abstract: This paper presents the design and the implementation of input/output (I/O) interface circuits for Gb/s-per-pin operation, fully compatible with low-voltage differential signaling (LVDS) standard. Due to the differential transmission technique and the low voltage swing, LVDS allows high transmission speeds and low power consumption at the same time. In the proposed transmitter, the required tolerance on the dc output levels was achieved over process, temperature, and supply voltage variations with neither external components nor trimming procedures, by means of a closed-loop control circuit and an internal voltage reference. The proposed receiver implements a dual-gain-stage folded-cascode architecture which allows a 1.2-Gb/s transmission speed with the minimum common-mode and differential voltage at the input. The circuits were implemented in a 3.3-V 0.35-/spl mu/m CMOS technology in a couple of test chips. Transmission operations up to 1.2 Gb/s with random data patterns and up to 2 Gb/s in asynchronous mode were demonstrated. The transmitter and receiver pad cells exhibit a power consumption of 43 and 33 mW, respectively.

208 citations

Patent
05 Mar 1997
TL;DR: In this paper, a scalable high performance ATM cell/packet switch (HiPAS) element for a shared memory switch fabric application is presented, which includes a PAC Bus (Packet/ATM Cell Bus) and the Switch Fabric Controller Bus (SC Bus).
Abstract: A scalable high performance ATM cell/packet switch (HiPAS) element for a shared memory switch fabric application. The switch element includes a PAC Bus (Packet/ATM Cell Bus) and the Switch Fabric Controller Bus (SC Bus). The HiPAS switch element receives and transmits the ATM cells/packets through the PAC Bus. The PAC Bus provides independent parallel datapaths for the receive port and transmit port. The PAC Bus provides a unique structural feature to the HiPAS switch element and allows expansion to the switch capacity in a manner similar to a bit-slice processor. Multiple number of HiPAS switch elements can be concatenated to expand the capacity. In the concatenated configuration, the datapaths of the receive port and transmit port are interleaved so that the interconnection remains point-to-point. As the result, all of the switch ports in the switch execute the cell transactions concurrently on the PAC Bus. In addition, each switch fabric port has a dedicated serial port to exchange status information between the switch fabric and the switch port adapter.

207 citations