Masahiko Takenaka

Bio: Masahiko Takenaka is an academic researcher from Fujitsu. The author has contributed to research in topics: Encryption & Authentication. The author has an hindex of 25, co-authored 279 publications receiving 2822 citations.

Address-Bit Differential Power Analysis of Cryptographic Schemes OK-ECDH and OK-ECDSA

Abstract: The differential power analysis (DPA) is a powerful attack against the implementation of cryptographic schemes on mobile devices. This paper proposes an alternative DPA using the addresses of registers of elliptic curve based cryptosystems (ECC) implemented on smart cards. We call the analysis the address-bit DPA in this paper. The analysis was originally investigated by Messerges, Dabbish and Sloan, however it was thought to be of no effect if the intermediate data are randomized. We extend the analysis and show how the extended analysis works against scalar exponentiations even if the implementation is resistant against the data-based DPA. We show experimental results of our analysis of cryptographic schemes OK-ECDH and OK-ECDSA, which are candidates of the CRYPTREC project in Japan, and evidence of their weakness.

Implementation of Elliptic Curve Cryptographic Coprocessor over GF(2m) on an FPGA

Abstract: We describe the implementation of an elliptic curve cryptographic (ECC) coprocessor over GF(2m) on an FPGA and also the result of simulations evaluating its LSI implementation. This coprocessor is suitable for server systems that require efficient ECC operations for various parameters. For speeding-up an elliptic scalar multiplication, we developed a novel configuration of a multiplier over GF(2m), which enables the multiplication of any bit length by using our data conversion method. The FPGA implementation of the coprocessor with our multiplier, operating at 3 MHz, takes 80 ms for 163-bit elliptic scalar multiplication on a pesudo-random curve and takes 45 ms on a Koblitz curve. The 0.25 µm ASIC implementation of the coprocessor, operating at 66 MHz and having a hardware size of 165 Kgates, would take 1.1 ms for 163-bit elliptic scalar multiplication on a pesudo-random curve and would take 0.65 ms on a Koblitz curve.

Fast Implementation of Public-Key Cryptography ona DSP TMS320C6201

Abstract: We propose new fast implementation method of public-key cryptography suitable for DSP. We improved modular multiplication and elliptic doubling to increase speed. For modular multiplication, we devised a new implementation method of Montgomery multiplication, which is suitable for pipeline processing. For elliptic doubling, we devised an improved computation for the number of multiplications and additions. We implemented RSA, DSA and ECDSA on the latest DSP (TMS320C6201, Texas Instruments), and achieved a performance of 11.7 msec for 1024- bit RSA signing, 14.5 msec for 1024-bit DSA verification and 3.97 msec for 160-bit ECDSA verification.

DPA Countermeasures by Improving the Window Method

Abstract: We propose three differential power analysis (DPA) countermeasures for securing the public key cryptosystems. All countermeasures are based on the window method, and can be used in both RSA and elliptic curve cryptosystems (ECC). By using the optimal countermeasure, performance penalty is small. In comparison with k-ary method, computation time of our countermeasure is only 105% in 1024-bit RSA and 119% in 160-bit ECC.

Implementation of Elliptic curve cryptographic coprocessor over GF(2m) on an FPGA

Abstract: We describe the implementation of an elliptic curve cryptographic (ECC) coprocessor over GF(2 m ) on an FPGA and also the result of simulations evaluating its LSI implementation This coprocessor is suitable for server systems that require efficient ECC operations for various parameters For speeding-up an elliptic scalar multiplication, we developed a novel configuration of a multiplier over GF(2 m ) which enables the multiplication of any bit length by using our data conversion method The FPGA implementation of the coprocessor with our multiplier, operating at 3 MHz, takes 80 ms for 163-bit elliptic scalar multiplication on a pesudo-random curve and takes 45 ms on a Koblitz curve The 025 pm ASIC implementation of the coprocessor, operating at 66 MHz and having a hardware size of 165 Kgates, would take 11 ms for 163-bit elliptic scalar multiplication on a pesudo-random curve and would take 065 ms on a Koblitz curve

Guide to Elliptic Curve Cryptography

Abstract: After two decades of research and development, elliptic curve cryptography now has widespread exposure and acceptance. Industry, banking, and government standards are in place to facilitate extensive deployment of this efficient public-key mechanism. Anchored by a comprehensive treatment of the practical aspects of elliptic curve cryptography (ECC), this guide explains the basic mathematics, describes state-of-the-art implementation methods, and presents standardized protocols for public-key encryption, digital signatures, and key establishment. In addition, the book addresses some issues that arise in software and hardware implementation, as well as side-channel attacks and countermeasures. Readers receive the theoretical fundamentals as an underpinning for a wealth of practical and accessible knowledge about efficient application. Features & Benefits: * Breadth of coverage and unified, integrated approach to elliptic curve cryptosystems * Describes important industry and government protocols, such as the FIPS 186-2 standard from the U.S. National Institute for Standards and Technology * Provides full exposition on techniques for efficiently implementing finite-field and elliptic curve arithmetic* Distills complex mathematics and algorithms for easy understanding* Includes useful literature references, a list of algorithms, and appendices on sample parameters, ECC standards, and software toolsThis comprehensive, highly focused reference is a useful and indispensable resource for practitioners, professionals, or researchers in computer science, computer engineering, network design, and network data security.

Quantized Neural Networks: Training Neural Networks with Low Precision Weights and Activations

Abstract: We introduce a method to train Quantized Neural Networks (QNNs) --- neural networks with extremely low precision (e.g., 1-bit) weights and activations, at run-time. At train-time the quantized weights and activations are used for computing the parameter gradients. During the forward pass, QNNs drastically reduce memory size and accesses, and replace most arithmetic operations with bit-wise operations. As a result, power consumption is expected to be drastically reduced. We trained QNNs over the MNIST, CIFAR-10, SVHN and ImageNet datasets. The resulting QNNs achieve prediction accuracy comparable to their 32-bit counterparts. For example, our quantized version of AlexNet with 1-bit weights and 2-bit activations achieves $51\%$ top-1 accuracy. Moreover, we quantize the parameter gradients to 6-bits as well which enables gradients computation using only bit-wise operation. Quantized recurrent neural networks were tested over the Penn Treebank dataset, and achieved comparable accuracy as their 32-bit counterparts using only 4-bits. Last but not least, we programmed a binary matrix multiplication GPU kernel with which it is possible to run our MNIST QNN 7 times faster than with an unoptimized GPU kernel, without suffering any loss in classification accuracy. The QNN code is available online.

Digital rights management in a mobile communications environment

Abstract: The invention provides a method, system, and computer program product to control the access, copying, and/or transfer of a digital asset by mobile, wireless devices using a digital voucher. The digital voucher references a primary content that contains all of the expression for that particular asset and a secondary content that contains information that can be distilled out as a preview. The information in the primary content can be limited to a specified duration or a specific number of viewings. The author, owner, or possessor of the digital asset specifies the terms and conditions for distribution of the digital asset. The digital voucher authorizes the mobile, wireless device to access a specified primary or secondary content that may be located elsewhere in the network. The mobile, wireless device can download a copy of portions or all of the content depending on the terms specified in the voucher.

System and method for processing financial transactions

Abstract: Disclosed herein are systems, methods, and non-transitory computer-readable storage media for receiving data from a giver at a first time, the data being used to identify a merchant at which a gift from the giver to a recipient is redeemable. The system presents a group of merchants associated with the data to the giver, each merchant of the group of merchants offering a promotion in connection with the gift. The system receives from the giver a selection of a chosen merchant from the group of merchants, the chosen merchant having an associated promotion. The system then generates a policy comprising the gift, the chosen merchant, and the associated promotion such that upon receiving an indication of a triggering event caused by the recipient, the system can apply the gift and the associated promotion according to the policy.

Rfid Handbook Fundamentals And Applications In Contactless Smart Cards And Identification

Abstract: Thank you for reading rfid handbook fundamentals and applications in contactless smart cards and identification. As you may know, people have search numerous times for their chosen novels like this rfid handbook fundamentals and applications in contactless smart cards and identification, but end up in malicious downloads. Rather than reading a good book with a cup of coffee in the afternoon, instead they juggled with some malicious bugs inside their laptop.