M
Masami Hane
Researcher at Renesas Electronics
Publications - 75
Citations - 941
Masami Hane is an academic researcher from Renesas Electronics. The author has contributed to research in topics: MOSFET & Ion implantation. The author has an hindex of 16, co-authored 75 publications receiving 903 citations. Previous affiliations of Masami Hane include NEC.
Papers
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Proceedings ArticleDOI
A 0.063 µm 2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
V. Basker,Theodorus E. Standaert,H. Kawasaki,C.-C. Yeh,Kingsuk Maitra,Tenko Yamashita,J. Faltermeier,H. Adhikari,Hemanth Jagannathan,Junli Wang,Hiroshi Sunamura,S. Kanakasabapathy,Stefan Schmitz,Jason E. Cummings,Atsuro Inada,Chung Hsun Lin,Pranita Kulkarni,Yu Zhu,J. Kuss,T. Yamamoto,Amit Kumar,Jeremy A. Wahl,Atsushi Yagishita,Lisa F. Edge,R. H. Kim,Erin Mclellan,S. Holmes,R. C. Johnson,T. Levin,James J. Demarest,Masami Hane,Mariko Takayanagi,Matthew E. Colburn,Vamsi Paruchuri,R. J. Miller,Huiming Bu,Bruce B. Doris,D. McHerron,Effendi Leobandung,James A. O’Neill +39 more
TL;DR: In this paper, the smallest FinFET SRAM cell size of 0.063 µm2 has been achieved using optical lithography using a double-expose, double-etch (DE2) sidewall image transfer (SIT) process.
Proceedings ArticleDOI
Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond
Qing Liu,Atsushi Yagishita,Nicolas Loubet,Ali Khakifirooz,Pranita Kulkarni,T. Yamamoto,Kangguo Cheng,M. Fujiwara,Jin Cai,D. Dorman,Swati Mehta,Prasanna Khare,K. Yako,Yu Zhu,S. M. Mignot,S. Kanakasabapathy,Stephane Monfray,Frederic Boeuf,Charles W. Koburger,Hiroshi Sunamura,Shom Ponoth,Alexander Reznicek,Balasubramanian S. Pranatharthi Haran,A. Upham,R. Johnson,Lisa F. Edge,J. Kuss,T. Levin,N. Berliner,Effendi Leobandung,Thomas Skotnicki,Masami Hane,Huiming Bu,Kazunari Ishimaru,Walter Kleemeier,Mariko Takayanagi,Bruce B. Doris,R. Sampson +37 more
TL;DR: In this paper, a gate length of 25nm and competitive drive currents of 1.27 mV·µm were achieved by using a gate-first high-k/metal and raised source/drains (RSD).
Proceedings Article
Sub-25nm FinFET with advanced fin formation and short channel effect engineering
Tenko Yamashita,V. Basker,Theodorus E. Standaert,C.-C. Yeh,T. Yamamoto,Kingsuk Maitra,C.-H. Lin,J. Faltermeier,S. Kanakasabapathy,Miaomiao Wang,H. Sunamura,Hemanth Jagannathan,Alexander Reznicek,Stefan Schmitz,A. Inada,Junli Wang,H. Adhikari,N. Berliner,K-L. Lee,Pranita Kulkarni,Yu Zhu,Amit Kumar,A. Bryant,S. Wu,Thomas S. Kanarsky,Jin Cho,Erin Mclellan,S. Holmes,R. C. Johnson,T. Levin,James J. Demarest,James Chingwei Li,Philip J. Oldiges,John C. Arnold,Matt Colburn,Masami Hane,D. McHerron,Vamsi Paruchuri,Bruce B. Doris,R. J. Miller,Huiming Bu,Mukesh Khare,James A. O’Neill,Effendi Leobandung +43 more
TL;DR: In this paper, a dual-work function gate-first process flow at 100 nm gate pitch and 40 nm fin pitch is demonstrated, achieving N/P Ion values of 1250/950 uA/m at 100nA/um at 1V, 1300/1000 uA /m with self-heating correction.
Proceedings ArticleDOI
Atomistic 3D process/device simulation considering gate line-edge roughness and poly-Si random crystal orientation effects [MOSFETs]
Masami Hane,T. Ikezawa,T. Ezaki +2 more
TL;DR: In this article, intrinsic statistical fluctuations in device characteristics were examined using newly developed simulation tools for the precise design of sub-100 nm MOSFETs, and ion implantation and subsequent dopant diffusion/activation were simulated based on Monte Carlo procedures.
Proceedings ArticleDOI
Highly reliable BEOL-transistor with oxygen-controlled InGaZnO and Gate/Drain offset design for high/low voltage bridging I/O operations
Kishou Kaneko,Naoya Inoue,S. Saito,N. Furutake,H. Sunamura,Jun Kawahara,Masami Hane,Yoshihiro Hayashi +7 more
TL;DR: In this article, a gate/drain offset structure was proposed to suppress hot-carrier generation, resulting in a stable operation at high V d bias condition (∼20V).