M
Masao Inoue
Researcher at Renesas Electronics
Publications - 55
Citations - 310
Masao Inoue is an academic researcher from Renesas Electronics. The author has contributed to research in topics: Threshold voltage & Gate dielectric. The author has an hindex of 9, co-authored 54 publications receiving 291 citations.
Papers
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Journal ArticleDOI
Mr Evaluation of Mediopatellar Plica
Katsuyuki Nakanishi,Masao Inoue,Takeshi Ishida,Takamichi Murakami,Kyo Tsuda,Junpei Ikezoe,Hironobu Nakamura +6 more
TL;DR: MR imaging is useful as a screening method for detecting MP before arthroscopy and for evaluating its extension, according to the Sakakibara classification of MP.
Proceedings ArticleDOI
Fluorine incorporation into HfSiON dielectric for V/sub th/ control and its impact on reliability for poly-Si gate pFET
Masao Inoue,Shimpei Tsujikawa,M. Mizutani,K. Nomura,T. Hayashi,K. Shiga,J. Yugami,Junichi Tsuchimoto,Y. Ohno,M. Yoneda +9 more
TL;DR: F incorporation into HfSiON dielectric using channel implantation technique is shown to be highly effective in lowering Vth and improving NBTI in poly-Si gate pFET as discussed by the authors.
Journal ArticleDOI
XPS Study of H-Terminated Silicon Surface under Inert Gas and UHV Annealing
Kazumasa Kawase,Junji Tanimura,Hiroshi Kurokawa,Kazutoshi Wakao,Masao Inoue,Hiroshi Umeda,Akinobu Teramoto +6 more
TL;DR: In this paper, the changes of chemical bonding states of an H-terminated silicon surface under inert gas (Ar,N 2 ) and ultrahigh vacuum (UHV) annealing using X-ray photoelectron spectroscopy (XPS) and thermal desorption (TDS) were investigated.
Journal ArticleDOI
Phosphorus and boron diffusion paths in polycrystalline silicon gate of a trench-type three-dimensional metal-oxide-semiconductor field effect transistor investigated by atom probe tomography
Bin Han,Hisashi Takamizawa,Yasuo Shimizu,Koji Inoue,Yasuyoshi Nagai,Fumiko Yano,Yorinobu Kunimune,Masao Inoue,Akio Nishida +8 more
TL;DR: In this paper, the dopant diffusion path in n-and p-types polycrystalline-Si gates of trench-type three-dimensional (3D) metal-oxide-semiconductor field effect transistors (MOSFETs) was investigated using atom probe tomography, based on the annealing time dependence of dopant distribution at 900°C.
Proceedings ArticleDOI
First demonstration of FinFET split-gate MONOS for high-speed and highly-reliable embedded flash in 16/14nm-node and beyond
Shibun Tsuda,Yoshiyuki Kawashima,Kenichiro Sonoda,Atsushi Yoshitomi,Tatsuyoshi Mihara,S. Narumi,Masao Inoue,Seiji Muranaka,Takahiro Maruyama,Tomohiro Yamashita,Yasuo Yamaguchi,Digh Hisamoto +11 more
TL;DR: In this article, a split-gate metal-oxide nitride oxide silicon (SG-MONOS) flash memory has been fabricated and operated for the first time, showing excellent sub-threshold characteristics and small threshold-voltage variability owing to a Fin-structure.