Masataka Ikeda

Bio: Masataka Ikeda is an academic researcher. The author has contributed to research in topics: Signal & Gate driver. The author has an hindex of 8, co-authored 16 publications receiving 1158 citations.

15.2: Development of Driver‐Integrated Panel Using Amorphous In‐Ga‐Zn‐Oxide TFT

Abstract: We designed, prototyped, and evaluated LCD integrated with a gate driver and a source driver using amorphous In-Ga-Zn-Oxide TFTs having bottom-gate bottom-contact structure, thereby obtaining TFTs with superior characteristics Then, we prototyped the world's first 4-inch QVGA LCD and integrated the gate driver and source driver on the display panel

Touch panel and method for manufacturing touch panel

Abstract: A touch panel capable of performing display and sensing along a curved surface or a touch panel that maintains high detection sensitivity even when it is curved along a curved surface is provided. A flexible display panel is placed along a curved portion included in a surface of a support. A first film layer is attached along a surface of the display panel by a bonding layer. Second to n-th film layers (n is an integer of 2 or more) are sequentially attached along a surface of the first film layer by bonding layers. A flexible touch sensor is attached along a surface of the n-th film layer by a bonding layer.

Development of Liquid Crystal Display Panel Integrated with Drivers Using Amorphous In–Ga–Zn-Oxide Thin Film Transistors

Abstract: We designed, prototyped, and evaluated a liquid crystal panel integrated with a gate driver and a source driver using amorphous In–Ga–Zn-oxide thin film transistors (TFTs). Using bottom-gate bottom-contact (BGBC) thin film transistors, superior characteristics could be obtained. We obtained TFT characteristics with little variation even when the thickness of the gate insulator (GI) film was reduced owing to etching of source/drain (S/D) wiring, which is a typical process for the BGBC TFT. Moreover, a favorable ON-state current was obtained even when an In–Ga–Zn-oxide layer was formed over the S/D electrode. Since the upper portion of the In–Ga–Zn-oxide layer is not etched, the BGBC structure is predicted to be effective in thinning the In–Ga–Zn-oxide layer in the future. Upon evaluation, we found that the prototyped liquid crystal panel integrated with the gate and source drivers using the TFTs with improved characteristics had stable drive.

30.9 Normally-off computing with crystalline InGaZnO-based FPGA

Abstract: An FPGA employing c-axis aligned crystal In-Ga-Zn oxide (CAAC-IGZO) FET [1] based configuration memories (CMs) is known to need no reconfiguration thanks to nonvolatile CMs, shows high operation speed due to boosting effect of pass gates used in routing switches (RS) [2], and easily realizes fine-grained multi-context (FG-MC) architecture [2] because CMs which need very low power to keep the contents can be constructed with a small number of transistors. It would be very difficult to realize all of these features in FPGAs using MRAM [3] or RRAM [4]. These features are very unique to the CAAC-IGZO FPGA.

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device and display device

Abstract: An object of the present invention is to decrease the resistance of a power supply line, to suppress a voltage drop in the power supply line, and to prevent defective display. A connection terminal portion includes a plurality of connection terminals. The plurality of connection terminals is provided with a plurality of connection pads which is part of the connection terminal. The plurality of connection pads includes a first connection pad and a second connection pad having a line width different from that of the first connection pad. Pitches between the plurality of connection pads are equal to each other.

Thin-film transistor

Abstract: A gate-insulated thin film transistor is disclosed. One improvement is that the thin film transistor is formed on a substrate through a blocking layer in between so that it is possible to prevent the transistor from being contaminated with impurities such as alkali ions which exist in the substrate. Also, a halogen is added to either or both of the blocking layer and a gate insulator of the transistor in order that impurities such as alkaline ions, dangling bonds and the like can be neutralized, therefore, the reliability of the device is improved.

Semiconductor display device

Abstract: To provide a semiconductor display device capable of displaying an image having clarity and a desired color, even when the speed of deterioration of an EL layer is influenced by its environment. Display pixels and sensor pixels of an EL display each have an EL element, and the sensor pixels each have a diode. The luminance of the EL elements of each in the display pixels is controlled in accordance with the amount of electric current flowing in each of the diodes.

Display device and manufacturing method thereof

Abstract: Disclosed is a display device including a transistor showing extremely low off current. In order to reduce the off current, a semiconductor material whose band gap is greater than that of a silicon semiconductor is used for forming a transistor, and the concentration of an impurity which serves as a carrier donor of the semiconductor material is reduced. Specifically, an oxide semiconductor whose band gap is greater than or equal to 2 eV, preferably greater than or equal to 2.5 eV, more preferably greater than or equal to 3 eV is used for a semiconductor layer of a transistor, and the concentration of an impurity which serves as a carrier donor included is reduced. Consequently, the off current of the transistor per micrometer in channel width can be reduced to lower than 10 zA/μm at room temperature and lower than 100 zA/μm at 85° C.