M
Masaya Miyahara
Researcher at Tokyo Institute of Technology
Publications - 111
Citations - 2027
Masaya Miyahara is an academic researcher from Tokyo Institute of Technology. The author has contributed to research in topics: CMOS & Amplifier. The author has an hindex of 21, co-authored 111 publications receiving 1689 citations. Previous affiliations of Masaya Miyahara include KEK.
Papers
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Proceedings ArticleDOI
A low-noise self-calibrating dynamic comparator for high-speed ADCs
TL;DR: In this paper, a low offset voltage, low noise dynamic latched comparator using a self-calibrating technique is presented, which does not require any amplifiers for the offset voltage cancellation and quiescent current.
Journal ArticleDOI
Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry
Kenichi Okada,Keitarou Kondou,Masaya Miyahara,Masashi Shinagawa,Hiroki Asada,Ryo Minami,T. Yamaguchi,Ahmed Eleojo Musa,Yuuki Tsukui,Yasuo Asakura,Shinya Tamonoki,Hiroyuki Yamagishi,Yasufumi Hino,Takashi Sato,Hironori Sakaguchi,N. Shimasaki,Toshihiko Ito,Yasuaki Takeuchi,Ning Li,Qinghong Bu,Rui Murakami,Keigo Bunsen,Kouta Matsushita,Makoto Noda,Akira Matsuzawa +24 more
TL;DR: This paper presents a 60-GHz direct-conversion RF front-end and baseband transceiver including analog and digital circuitry for PHY functions, capable of more than 7-Gb/s 16QAM wireless communication for every channel of the 60- GHz standards, which can be extended up to 10 Gb/s.
Journal ArticleDOI
64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay
Rui Wu,Ryo Minami,Yuuki Tsukui,Seitaro Kawai,Yuuki Seo,Shinji Sato,Kento Kimura,Satoshi Kondo,Tomohiro Ueno,Nurul Fajri,Shoutarou Maki,Noriaki Nagashima,Yasuaki Takeuchi,Tatsuya Yamaguchi,Ahmed Eleojo Musa,Korkut Kaan Tokgoz,Teerachot Siriburanon,Bangan Liu,Yun Wang,Jian Pang,Ning Li,Masaya Miyahara,Kenichi Okada,Akira Matsuzawa +23 more
TL;DR: This paper presents 64-quadrature amplitude modulation (QAM) 60-GHz CMOS transceivers with four-channel bonding capability, which can be categorized into a one-stream transceiver and a two-stream frequency-interleaved (FI) transceiver.
Journal ArticleDOI
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration
Ahmed Eleojo Musa,Wei Deng,Teerachot Siriburanon,Masaya Miyahara,Kenichi Okada,Akira Matsuzawa +5 more
TL;DR: The IL-ADPLL is implemented in a 65 nm CMOS process and measurement results show that it achieves a 0.7ps RMS jitter at 1.2 GHz while having 1.6 mW and 0.97 mW power consumption with and without intermittent operation resulting in an FOM of -243 dB.
Proceedings ArticleDOI
A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry
Kenichi Okada,Keitarou Kondou,Masaya Miyahara,Masashi Shinagawa,Hiroki Asada,Ryo Minami,Tatsuya Yamaguchi,Ahmed Eleojo Musa,Yuuki Tsukui,Yasuo Asakura,Shinya Tamonoki,Hiroyuki Yamagishi,Yasufumi Hino,Takahiro Sato,Hironori Sakaguchi,Naoki Shimasaki,Toshihiko Ito,Yasuaki Takeuchi,Ning Li,Qinghong Bu,Rui Murakami,Keigo Bunsen,Kota Matsushita,Makoto Noda,Akira Matsuzawa +24 more
TL;DR: This paper presents a 60 GHz direct-conversion front-end and baseband transceiver, including analog and digital circuitry for the PHY functions, and is capable of more than 7 Gb/s 16QAM wireless communication for every channel of the 60 GHz standards.