Masayuki Iwami

TL;DR: In this article, a semiconductor electronic device comprises a substrate; a buffer layer formed on the substrate, the buffer layer including not less than two layers of composite layer, in which a first semiconductor layer formed of a nitride-based compound semiconductor, having a lattice constant smaller than a substrate and a thermal expansion coefficient larger than a thermalexpansion coefficient of the substrate; and an intermediate layer provided between the substrate and buffer layer, the intermediate layer being formed by a polysilicon-based semiconductor having a linear combination of lattice constants smaller than the first

Abstract: A vertical semiconductor element comprises: an electro-conductive substrate; a GaN layer, as a nitride compound semiconductor layer, which is selectively grown as a convex shape on one surface of the electro-conductive substrate through a buffer layer; a source electrode as a first electrode formed on the GaN layer; and a drain electrode as a second electrode formed on another surface of the electro-conductive substrate.

TL;DR: In this paper, an enhancement-mode n-channel GaN-based hybrid MOS-HFET was demonstrated on AlGaN/GaN heterostructure on silicon substrates with a large drain current operation.

TL;DR: In this article, an active layer of a GaN-based semiconductor is formed on a silicon substrate and a trench is formed in the active layer and extends from a top surface of active layer to a depth reaching the silicon substrate.

TL;DR: In this paper, the threading dislocation extending from the lower layer area to the upper layer area is bent at the boundary surface of the substrate, and the dislocation reducing layer is formed in a location between a location directly under the buffer layer and inner area of the operating layer.