Massimo Gottardi

Bio: Massimo Gottardi is an academic researcher from fondazione bruno kessler. The author has contributed to research in topics: Pixel & CMOS. The author has an hindex of 19, co-authored 113 publications receiving 1268 citations. Previous affiliations of Massimo Gottardi include National Research Council & University of Trento.

Novel CMOS image sensor with a 132-dB dynamic range

Abstract: A CMOS image sensor providing an ultrawide dynamic range with a piecewise linear response is presented. The active pixel is based on a novel architecture which implements a voltage comparator and an analog memory to detect and store the information on the integration time needed to reach saturation, while also maintaining the standard integrated photo-current signal. A 128/spl times/64 pixel array has been designed and fabricated in 0.35-/spl mu/m, 3.3-V CMOS technology. The chip measures 2.67/spl times/4.90 mm/sup 2/ with a pixel size of 24.65/spl times/24.65 /spl mu/m/sup 2/ and a fill factor of about 11%. The sensor has been fully characterized and the measured dynamic range turned out to be 132 dB with a power consumption of 14 mW at video frame rate. The sensor features also good noise performance with a temporal noise of 0.2% (1.7%) and a fixed pattern noise of 0.4% (1.5%) at low (high) irradiance.

A 100 $\mu$ W 128 $\times$ 64 Pixels Contrast-Based Asynchronous Binary Vision Sensor for Sensor Networks Applications

Abstract: An ultra-low power 128 times 64 pixels vision sensor is here presented, featuring pixel-level spatial contrast extraction and binarization. The asynchronous readout only dispatches the addresses of the asserted pixels in bursts of 80 MB/s, significantly reducing the amount of data at the output. The pixel-embedded binary frame buffer allows the sensor to directly process visual information, such as motion and background subtraction, which are the most useful filters in machine vision applications. The presented sensor consumes less than 100 muW at 50 fps with 25% of pixel activity. Power consumption can be further reduced down to about 30 muW by operating the sensor in Idle-Mode, thus minimizing the sensor activity at the ouput.

A 33 $\mu$ W 64 $\,\times\,$ 64 Pixel Vision Sensor Embedding Robust Dynamic Background Subtraction for Event Detection and Scene Interpretation

Abstract: A 64 × 64-pixel ultra-low power vision sensor is presented, performing pixel-level dynamic background subtraction as the low-level processing layer of an algorithm for scene interpretation. The pixel embeds two digitally-programmable Switched-Capacitors Low-Pass Filters (SC-LPF) and two clocked comparators, aimed at detecting any anomalous behavior of the current photo-generated signal with respect to its past history. The 45 T, 26 μm square pixel has a fill-factor of 12%. The vision sensor has been fabricated in a 0.35 μm 2P3M CMOS process, powered with 3.3 V, and consumes 33 μ W at 13 fps, which corresponds to 620 pW/frame.pixel.

A 828μW 1.8V 80dB dynamic-range readout interface for a MEMS capacitive microphone

Abstract: A CMOS interface for a piston-type MEMS capacitive microphone is presented. It performs a capacitance-to-voltage conversion by bootstrapping the sensor through a voltage pre-amplifier, feeding a third-order sigma-delta modulator. The bootstrapping performs active parasitic compensation, improving the readout sensitivity by ~12 dB. The total current consumption is 460 uA at 1.8 V-supply. The digital output achieves 80 dBA-DR, with 63 dBA peak-SNR, using 0.35 um 2P/4M CMOS technology. The paper includes electrical and acoustic measurement results for the interface.

A CMOS smart pixel for active 3-D vision applications

Abstract: A CMOS smart pixel aimed at three-dimensional vision applications is introduced. It is suitable for scannerless laser ranging systems which employ the indirect time-of-flight measuring technique to recover distance information. The pixel is operated with trains of light pulses generated by an external source to illuminate the scene and contains most of the processing electronics to perform signal accumulation and noise reduction operations. The smart pixel architecture includes an N-well photodiode plus a self-biasing voltage amplifier and a switched-capacitor fully differential stage. The pixel is fabricated in standard CMOS 0.6 /spl mu/m technology and measures 180/spl times/160 /spl mu/m/sup 2/ (including the photodiode) with a fill factor of 14%. Electrooptical test results confirm the smart pixel functionality in a range of distance from 3 m to 9 m, and the accuracy achieved for preliminary distance measurements is 15 cm. Both the accuracy and the extension of the range of distance are supposed to be improved by reducing setup and environmental noise contributions that limit the pixel performance.

CMOS image sensors: electronic camera-on-a-chip

Abstract: CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.

CMOS image sensors

Abstract: In this article, we provide a basic introduction to CMOS image-sensor technology, design and performance limits and present recent developments and future directions in this area. We also discuss image-sensor operation and describe the most popular CMOS image-sensor architectures. We note the main non-idealities that limit CMOS image sensor performance, and specify several key performance measures. One of the most important advantages of CMOS image sensors over CCDs is the ability to integrate sensing with analog and digital processing down to the pixel level. Finally, we focus on recent developments and future research directions that are enabled by pixel-level processing, the applications of which promise to further improve CMOS image sensor performance and broaden their applicability beyond current markets.

CMOS image sensors: Electronic camera-on-a-chip

Abstract: CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.

On Spike-Timing-Dependent-Plasticity, Memristive Devices, and Building a Self-Learning Visual Cortex

Abstract: In this paper we present a very exciting overlap between emergent nano technology and neuroscience. We are linking one type of memristor nano technology devices to the biological synaptic update rule known as Spike-Time-Dependent-Plasticity found in real biological synapses. Understanding this link allows neuromorphic engineers to develop circuit architectures that use this type of memristors to artificially emulate parts of the visual cortex. We focus on the type of memristors referred to as voltage driven memristors and focus our discussions on a behavioral macro model for such devices. The implementations result in fully asynchronous architectures with neurons sending their action potentials not only forwards but also backwards. One critical aspect is to use neurons that generate spikes of specific shapes. By changing the shapes of the neuron action potential spikes we can tune and manipulate the STDP learning rules for both excitatory and inhibitory synapses. We show how neurons and memristors can be interconnected to achieve large scale spiking learning systems, that follow a type of multiplicative STDP learning rule. We briefly extend the architectures to use three-terminal transistors with similar memristive behavior. We illustrate how a V1 visual cortex layer can assembled and how it is capable of learning to extract orientations from visual data coming from a real artificial CMOS spiking retina observing real life scenes. Finally, we discuss limitations of currently available memristors. The results presented are based on behavioral simulations and do not take into account non-idealities of devices and interconnects. The aim of this paper is to present, in a tutorial manner, an initial framework for the possible development of fully asynchronous STDP learning neuromorphic architectures exploiting two or three terminal memristive type devices. All files used for the simulations are made available through the journal web site.