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Showing papers by "Massoud Pedram published in 1991"


Proceedings ArticleDOI
01 Jun 1991
TL;DR: Lily, a technology mapper integrated with MIS, which considers layout area and wire delay during the technology dependent phase of logic synthesis, and estimates the interconnection dependent contributions to circuit area and delay by referring to a dynamically updated global placement of the Boolean network.
Abstract: Recent studies indicate that interconnections occupy more than half the total chip area and account for a significant part of the chip delay. In spite of this, most logic synthesis systems do not explicitly take the wiring into account during the optimization phase. Our work is a first step towards including wiring into the logic synthesis process. In this paper, we present Lily, a technology mapper integrated with MIS, which considers layout area and wire delay during the technology dependent phase of logic synthesis. Lily estimates the interconnection dependent contributions to circuit area and delay by referring to a dynamically updated global placement of the Boolean network. The update does not restrict the dynamic programming approach adopted in technology mappers such as DAGON and MIS. Our algorithm has been implemented and preliminary results are encouraging.

134 citations


Proceedings ArticleDOI
11 Nov 1991
TL;DR: The authors present techniques to integrate interconnection optimization with logic restructuring and technology decomposition phases of logic synthesis, based on a point placement of a Boolean network which is used to guide the synthesis process by providing accurate estimates on wiring area and delay.
Abstract: The authors present techniques to integrate interconnection optimization with logic restructuring and technology decomposition phases of logic synthesis. The approach is based on a point placement of a Boolean network which is used to guide the synthesis process by providing accurate estimates on wiring area and delay. The placement solution is incrementally updated as intermediate Boolean nodes are extracted or eliminated during the decomposition or elimination procedures. Combining these techniques with layout-driven technology mapping makes it possible to produce a synthesis solution and a 'companion' placement solution for a given combinational logic circuit simultaneously. Using these techniques, circuits with smaller area and higher performance can be generated. >

70 citations


Proceedings ArticleDOI
14 Oct 1991
TL;DR: Experimental data show that as a result of using the I/O pad assignment procedure, the total interconnection length and circuit delay are reduced by 8-15% and 3-4%, respectively.
Abstract: An algorithm is presented for assigning off-chip I/O pads for a logic circuit. The technique, which is based on the analysis of the circuit structure and path delay constraints, uses linear placement, goal-programming, linear-sum assignment and I/O pad clustering to assign locations to I/O pads. The I/O pad assignment is then used by placement tools. Experimental data show that as a result of using the I/O pad assignment procedure, the total interconnection length and circuit delay (after placement and routing) are reduced by 8-15% and 3-4%, respectively. This technique is general and can handle I/O pad assignment prior to logic synthesis or detailed placement procedures. >

25 citations