Showing papers by "Massoud Pedram published in 1992"
TL;DR: In this paper, a hierarchical floorplan planning approach for macrocell layouts is presented, which is based on the bottom-up clustering, shape function computation, and top-down floorplan optimization with integrated global routing and pin assignment.
Abstract: This paper presents a hierarchical floorplanning approach for macrocell layouts which is based on the bottom-up clustering, shape function computation, and top-down floorplan optimization with integrated global routing and pin assignment. This approach provides means for specifying and techniques for satisfying a wide range of constraints (physical, topological, timing) and is, therefore, able to generate floorplans for a number of different layout styles. A systematic and efficient optimization procedure during the selection of suitable floorplan patterns that integrates floorplanning, global routing and pin assignment, a new pin assignment technique based on linear assignment and driven by the global routing solution and floorplan topology, and an effective timing-driven floorplanning scheme are among the other novel features of the floorplanner. These techniques have been incorporated in BEAR-FP, a macrocell layout system developed at the University of California, Berkeley. Results on various placement and floorplanning benchmarks are quite good.
8 citations
01 Nov 1992
TL;DR: These techniques can be used to merge FSMs that control the functional and test circuitry in the data path that have on average 20% less factored form literals than the machines produced by an existing state minimizer.
Abstract: The authors present techniques for merging a pair of finite state machines (FSMs) that control the data-path circuitry on a chip In particular, these techniques can be used to merge FSMs that control the functional and test circuitry in the data path An A* algorithm is used to obtain the state transition table of the merged controller, and then standard synthesis tools are used for state assignment and logic minimization The procedure targets either two-level or multilevel logic implementation Compared to implementing the functional and test controllers separately, it is shown that merging the controllers leads to significant savings in logic area For multilevel implementation, the technique produces merged machines that have on average 20% less factored form literals than the machines produced by an existing state minimizer >
6 citations