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Showing papers by "Massoud Pedram published in 1995"


Proceedings ArticleDOI
01 Jan 1995
TL;DR: Experimental results confirm the viability and usefulness of the approach in minimizing power consumption during the register assignment phase of the behavioral synthesis process.
Abstract: This paper describes a technique for calculating the switching activity of a set of registers shared by different data values. Based on the assumption that the joint pdf (probability density function) of the primary input random variables is known or that a suffficiently large number of input vectors has been given, the register assignment problem for minimum power consumption is formulated as a minimum cost clique covering of an appropriately defined compatibility graph (which is shown to be transitively orientable). The problem is then solved optimally (in polynomial time) using a max-cost ow algorithm. Experimental results confirm the viability and usefulness of the approach in minimizing power consumption during the register assignment phase of the behavioral synthesis process.

190 citations


Journal ArticleDOI
01 Jan 1995
TL;DR: The CAD tools and methodologies required to effect efficient design for low power are described in the form of a tutorial and an attempt is made to provide commercial CAD tool vendors with an understanding of the needs and time frames for new CAD tools supporting low power design.
Abstract: Power consumption is rapidly becoming an area of growing concern in IC and system design houses. Issues such as battery life, thermal limits, packaging constraints and cooling options are becoming key factors in the success of a product. As a consequence, IC and system designers are beginning to see the impact of power on design area, design speed, design complexity and manufacturing cost. While process and voltage scaling can achieve significant power reductions, these are expensive strategies that require industry momentum, that only pay off in the long run. Technology independent gains for power come from the area of design for low power which has a much higher return on investment (ROI). But low power design is not only a new area but is also a complex endeavour requiring a broad range of synergistic capabilities from architecture/microarchitecture design to package design. It changes traditional IC design from a two-dimensional problem (Area/performance) to a three-dimensional one (Area/Performance/Power). This paper describes the CAD tools and methodologies required to effect efficient design for low power. It is targeted to a wide audience and tries to convey an understanding of the breadth of the problem. It explains the state of the art in CAD tools and methodologies. The paper is written in the form of a tutorial, making it easy to read by keeping the technical depth to a minimum while supplying a wealth of technical references. Simultaneously the paper identifies unresolved problems in an attempt to incite research in these areas. Finally an attempt is made to provide commercial CAD tool vendors with an understanding of the needs and time frames for new CAD tools supporting low power design. >

182 citations


Journal ArticleDOI
TL;DR: This work describes a comprehensive framework for exact and approximate switching activity estimation in a sequential circuit and shows that the approximation scheme is within 1-3% of the exact method, but is orders of magnitude faster for large circuits.
Abstract: Recently developed methods for power estimation have primarily focused on combinational logic. We present a framework for the efficient and accurate estimation of average power dissipation in sequential circuits. Switching activity is the primary cause of power dissipation in CMOS circuits. Accurate switching activity estimation for sequential circuits is considerably more difficult than that for combinational circuits, because the probability of the circuit being in each of its possible states has to be calculated. The Chapman-Kolmogorov equations can be used to compute the exact state probabilities in steady state. However, this method requires the solution of a linear system of equations of size 2/sup N/ where N is the number of flip-flops in the machine. We describe a comprehensive framework for exact and approximate switching activity estimation in a sequential circuit. The basic computation step is the solution of a nonlinear system of equations which is derived directly from a logic realization of the sequential machine. Increasing the number of variables or the number of equations in the system results in increased accuracy. For a wide variety of examples, we show that the approximation scheme is within 1-3% of the exact method, but is orders of magnitude faster for large circuits. Previous sequential switching activity estimation methods can have significantly greater inaccuracies. >

144 citations


Proceedings ArticleDOI
01 Jan 1995
TL;DR: The relationship between logic and probabilistic domains is investigated and two new concepts - conditional independence and isotropy of signals - are brought into attention and a sufficient condition for analyzing complex dependencies is given.
Abstract: Power estimation in combinational modules is addressed from a probabilistic point of view. The zero-delay hypothesis is considered and under highly correlated input streams, the activities at the primary outputs and all internal nodes are estimated. For the first time, the relationship between logic and probabilistic domains is investigated and two new concepts - conditional independence and isotropy of signals - are brought into attention. Based on them, a sufficient condition for analyzing complex dependencies is given. In the most general case, the conditional independence problem has been shown to be NP-complete and thus appropriate heuristics are presented to estimate switching activity. Detailed experiments demonstrate the accuracy and efficiency of the method. The results reported here are useful in low power design.

100 citations


Proceedings ArticleDOI
23 Apr 1995
TL;DR: It is shown that the average switching activity can be predicted without simulation using either entropy or informational energy averages, and two new measures relying on these concepts are developed.
Abstract: The problem of estimating the energy consumption at register transfer level is addressed from an information theoretical point of view. It is shown that the average switching activity can be predicted without simulation using either entropy or informational energy averages. Consequently, two new measures relying on these concepts are developed. The accuracy of these models is investigated using common benchmarks and the results are promising.

82 citations


01 Jan 1995
TL;DR: The many issues facing designers at architectural, logic, circuit and device levels are described and some of the techniques that have been proposed to overcome these difficulties are presented.
Abstract: Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift where power dissipation has become as important a consideration as performance and area. This article reviews various strategies and methodologies for designing low power circuits and systems. It describes the many issues facing designers at architectural, logic, circuit and device levels and presents some of the techniques that have been proposed to overcome these difficulties. The article concludes with the future challenges that must be met to design low power, high performance systems.

59 citations


Proceedings ArticleDOI
01 Jan 1995
TL;DR: Algebraic procedures for node extraction and factorization that target low power consumption and it is shown that using the proposed SOP power cost function, all extractions resulting in a power reduction will not result in an increase in the number of literals in the network.
Abstract: This paper describes algebraic procedures for node extraction and factorization that target low power consumption. New power cost functions are introduced for the sum-of-products and factored form representations of functions. These cost functions are then used to guide the power optimization procedures. It is also shown that using the proposed SOP power cost function, all extractions resulting in a power reduction will not result in an increase in the number of literals in the network. The procedures described in this paper were implemented and results show 16% average improvement in power at the cost of 7% average increase in area.

44 citations


Proceedings ArticleDOI
01 Dec 1995
TL;DR: The feasibility of generating the set of all PPIs and the increased complexity of solving the minimum covering problem are analyzed by deriving an upper bound on the expected number of PPIs which shows it to be linearly proportional to the number of prime implicants of the function.
Abstract: We study the problem of two-level logic minimization for low power in static CMOS circuits. We start by defining Power Prime Implicants (PPIs) which identify the set of all implicants that are sufficient and necessary for obtaining a minimum power solution. We then provide an efficient algorithm for generating the set of all PPIs of a function. The set of all PPIs is then used in a minimum covering problem to find the best power solution. The feasibility of generating the set of all PPIs and the increased complexity of solving the minimum covering problem are analyzed by deriving an upper bound on the expected number of PPIs which shows it to be linearly proportional to the number of prime implicants of the function. The results of our experiments are then used to draw conclusions on the effectiveness of low power two-level logic minimization.

27 citations


Proceedings ArticleDOI
01 Jan 1995
TL;DR: Experimental results obtained with these routing cost functions are presented and discussed in detail and the effectiveness of each cost function is compared against the conventional literal savings cost function.
Abstract: This paper describes techniques for reducing the routing cost during logic extraction. Two routing cost functions derived from the global structure of a boolean network are analyzed and the effectiveness of each cost function is compared against the conventional literal savings cost function. Experimental results obtained with these routing cost functions are presented and discussed in detail.

24 citations


Proceedings ArticleDOI
01 Dec 1995
TL;DR: The algorithm provides a formal mechanism which implicitly enumerates alternate partitionings and selects a partitioning that has the same delay but less power dissipation, and produces delay and power optimal partitioning.
Abstract: In this paper, a delay optimal clustering/partitioning algorithm for minimizing the power dissipation of a circuit is proposed. Traditional approaches for delay optimal partitioning are based on Lawler's clustering algorithm that makes no attempt to explore alternative partitioning solutions that have the same delay but better power implementations. Our algorithm provides a formal mechanism which implicitly enumerates alternate partitionings and selects a partitioning that has the same delay but less power dissipation. For tree circuits, the proposed algorithm produces delay and power optimal partitioning whereas for non-tree circuits it produces delay optimal partitioning with significantly improved power dissipation.

21 citations


Proceedings ArticleDOI
02 Oct 1995
TL;DR: A cost function which can be used to minimize the routing contribution of a circuit during logic synthesis, instead of estimating the absolute routing cost of a net, captures the relative routing costs of nets based on the number of terminals on the nets.
Abstract: We present a cost function which can be used to minimize the routing contribution of a circuit during logic synthesis. Instead of estimating the absolute routing cost of a net, this function captures the relative routing costs of nets based on the number of terminals on the nets. Unlike the routing cost functions proposed earlier, the proposed cost function does not require layout-parameters or any tuning of the variables to achieve acceptable estimation of the routing cost. The usefulness of the proposed routing cost is verified by minimizing it during the process of logic extraction in logic synthesis, leading to an average of 10% improvement in the routing area and 8% improvement in the chip area at no performance loss.

Proceedings ArticleDOI
01 Jan 1995
TL;DR: A new method to solve the graph embedding problem which is the main step in the state assignment process is presented, to place the state adjacency graph in a two-dimensional grid while minimizing the total wire length.
Abstract: This paper addresses the problem of state assignment for large Finite State Machines (FSM). This is an important problem in the high performance digital system design where added functionality often comes at the expense of a larger (and slower) FSM to control the system. We present a new method to solve the graph embedding problem which is the main step in the state assignment process. The basic idea is to place the state adjacency graph in a two-dimensional grid while minimizing the total wire length. The grid is then mapped into an n-dimensional hypercube while nearly preserving the adjacency relations that is with dilation at most 2. Experimental results are presented and compared with those of NOVA.

Proceedings ArticleDOI
28 Apr 1995
TL;DR: This paper addresses the problem of partitioning a large PLA into a number of smaller PLA's (sub-PLA's) such that the total area of these sub- PLA's is minimum and the cycle time of the partitioned circuit is minimized.
Abstract: This paper addresses the problem of partitioning a large PLA into a number of smaller PLA's (sub-PLA's) such that the total area of these sub-PLA's is minimum and the cycle time of the partitioned circuit is minimized. First, we describe an iterative improvement method that deals with the case that sub-PLA's assume arbitrary sizes. Second, we present a partitioning technique based on fuzzy logic that deals with the case that the sizes of the sub-PLA's are fixed. Finally, we describe a method that considers not only delay through each sub-PLA, but also loading of sub-PLA's on the stage that is driving them. These techniques have been implemented and significantly outperformed conventional PLA partitioning schemes.

Proceedings ArticleDOI
01 Jan 1995
TL;DR: This panel seeks to expose solutions that designers and EDA vendors have, to present proper vehicles for transferring the low power design techniques and methodologies to the user community, and to provide a forum for exploring what is still needed.
Abstract: Mobile and portable information systems are pushing electronics and the development process In their wake are new requirements that drive low-power design This is however by no means the only driving force behind the need for a dramatic reduction of power dissipation in digital ICs There also exists a strong demand on producers of high end products to reduce power consumption Power minimization is thus vital for different reasons in different applications Design knowledge and experience in minimizing power while optimizing performance is very limited Low-power design is in its infancy The same can be said for design tools The opportunities for ultra low power tools and methodologies that achieve dramatic reduction of power and push higher up the design entry point are all around us However, the need for tools that broaden the low-power design envelope is not being articulated by the user community very strongly This panel seeks to expose solutions that designers and EDA vendors have, to present proper vehicles for transferring the low power design techniques and methodologies to the user community, and to provide a forum for exploring what is still needed What design paradigms make sense, what levels of accuracy and speed are acceptable to the users and what tools have the highest payoff are part of what this panel is all about