Showing papers by "Massoud Pedram published in 2008"

Probabilistic error propagation in logic circuits using the Boolean difference calculus

Abstract: A gate level probabilistic error propagation model is presented which takes as input the Boolean function of the gate, the signal and error probabilities of the gate inputs, and the gate error probability and produces the error probability at the output of the gate. The presented model uses the Boolean difference calculus and can be applied to the problem of calculating the error probability at the primary outputs of a multi-level Boolean circuit with a time complexity which is linear in the number of gates in the circuit. This is done by starting from the primary inputs and moving toward the primary outputs by using a post-order traversal. Experimental results demonstrate the accuracy and efficiency of the proposed approach compared to the other known methods for error calculation in VLSI circuits.

Leakage Minimization of SRAM Cells in a Dual- $V_t$ and Dual- $T_{\rm ox}$ Technology

Abstract: Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicrometer regime. As a result, reducing the subthreshold and tunneling gate leakage currents has become one of the most important criteria in the design of VLSI circuits. This paper presents a method based on dual- V t and dual- T ox assignment to reduce the total leakage power dissipation of static random access memories (SRAMs) while maintaining their performance. The proposed method is based on the observation that read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. Thus, the idea is to deploy different configurations of six-transistor SRAM cells corresponding to different threshold voltage and oxide thickness assignments for the transistors. Unlike other techniques for low-leakage SRAM design, the proposed technique incurs neither area nor delay overhead. In addition, it results in a minor change in the SRAM design flow. The leakage saving achieved by using this technique is a function of the values of the high threshold voltage and the oxide thickness, as well as the number of rows and columns in the cell array. Simulation results with a 65-nm process demonstrate that this technique can reduce the total leakage power dissipation of a 64 times 512 SRAM array by 33% and that of a 32 times 512 SRAM array by 40%.

NBTI-aware flip-flop characterization and design

Abstract: With the scaling down of the CMOS technologies, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the corresponding reduction in the long-term reliability of CMOS circuits. This paper investigates the effect of NBTI phenomenon on the setup and hold times of flip-flops. First, it is shown that NBTI tightens the setup and hold timing constraints imposed on the flip-flops in the design. Second, different types of flip-flops exhibit different levels of susceptibility to NBTI-induced change in their setup/hold time values. Finally, an NBTI-aware transistor sizing technique can minimize the NBTI effect on timing characteristics of the flip-flops.

Stochastic modeling of a thermally-managed multi-core system

Abstract: Achieving high performance under a peak temperature limit is a first-order concern for VLSI designers. This paper presents a new abstract model of a thermally-managed system, where a stochastic process model is employed to capture the system performance and thermal behavior. We formulate the problem of dynamic thermal management (DTM) as the problem of minimizing the energy cost of the system for a given level of performance under a peak temperature constraint by using a controllable Markovian decision process (MDP) model. The key rationale for utilizing MDP for solving the DTM problem is to manage the stochastic behavior of the temperature states of the system under online re-configuration of its micro-architecture and/or dynamic voltage-frequency scaling. Experimental results demonstrate the effectiveness of the modeling framework and the proposed DTM technique.

A current source model for CMOS logic cells considering multiple input switching and stack effect

Abstract: This paper presents a current source model (CSM) of a CMOS logic cell, which captures simultaneous switching of multiple inputs while accounting for the effect of internal node voltages of the logic cell. Characterization procedures for various components of the proposed CSM are described and application of the model to output waveform computation is discussed. Experimental results to assess the accuracy and efficiency of the proposed multiple input switching CSM in the context of noise and timing analyses in VLSI circuits are reported.

Charge Recycling in Power-Gated CMOS Circuits

Abstract: The design of a suitable power gating (e.g., multithreshold or super cutoff CMOS) structure is an important and challenging task in sub-90-nm very large scale integration (VLSI) circuits where leakage currents are significant. In designs where the mode transitions are frequent, a significant amount of energy is consumed to turn on or off the power gating structure. It is thus desirable to develop a power gating solution that minimizes the energy consumed during mode transitions. This paper presents such a solution by recycling charge between the virtual power and ground rails immediately after entering the sleep mode and just before wakeup. The proposed method can save up to 43% of the dynamic energy wasted during mode transition while maintaining the wakeup time of the original circuit. It also reduces the peak negative voltage value and the settling time of the ground bounce.

Coarse-grain MTCMOS sleep transistor sizing using delay budgeting

Abstract: Power gating is one of the most effective techniques in reducing the standby leakage current of VLSI circuits. In this paper we introduce a new approach for sleep transistor sizing which minimizes the total sleep transistor width for a coarse-grain multi-threshold CMOS circuit assuming a given standard cell and sleep transistor placement. First, the circuit is decomposed into a set of modules, each containing the set of logic cells that are closest to a sleep transistor cell. Next given an upper bound on the overall circuit speed degradation, the global timing slack is distributed among different clusters using a delay-budgeting. The slack distribution result is then used to size the sleep transistors such that the total sleep transistor width is minimized while accounting for the parasitic resistances of the virtual ground net. Results show that the proposed sizing algorithm produces sleep transistor sizes that are 40% smaller than those produced by previous approaches.

Statistical timing analysis of flip-flops considering codependent setup and hold times

Abstract: Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for employing SSTA is the characterization of the setup and hold times of the latches and flip-flops in the cell library. This paper presents a methodology to exploit the statistical codependence of the setup and hold times. The approach comprises of three steps. In the first step, probability mass function (pmf) of codependent setup and hold time (CSHT) contours are approximated with piecewise linear curves by considering the probability density functions of sources of variability. In the second step, pmf of the required setup and hold times for each flip-flop in the design are computed. Finally, these pmf values are used to compute the probability of individual flip-flops in the design passing the timing constraints and to report the overall pass probability of the flip-flops in the design as a histogram. We applied the proposed method to true single phase clocking flip-flops to generate the piecewise linear curves for CSHT. The characterized flip-flops were instantiated in an example design, on which timing verification was successfully performed.

Improving the Efficiency of Power Management Techniques by Using Bayesian Classification

Abstract: This paper presents a supervised learning based dynamic power management (DPM) framework for a multicore processor, where a power manager (PM) learns to predict the system performance state from some readily available input features (such as the state of service queue occupancy and the task arrival rate) and then uses this predicted state to look up the optimal power management action from a pre-computed policy lookup table. The motivation for utilizing supervised learning in the form of a Bayesian classifier is to reduce overhead of the PM which has to recurrently determine and issue voltage-frequency setting commands to each processor core in the system. Experimental results reveal that the proposed Bayesian classification based DPM technique ensures system-wide energy savings under rapidly and widely varying workloads.

Modulation-aware energy balancing in hierarchical wireless sensor networks

Abstract: Wireless sensor networks (WSN) with hierarchical organizations have recently attracted a lot of attention as effective platforms for pervasive computing. With power efficiency and lifetime awareness becoming critical design concerns, a significant amount of research has focused on energy-aware design of different layers of the WSN protocol stack. However, much less has been done in way of incorporating physical layer characteristics at the system deployment stage and analyzing the effects on spatial energy balancing across the network and the resulting overall network lifetime. Our focus is on improving the lifetime of each cluster of sensors in a hierarchical WSN using optimization techniques at the physical layer. Specifically, we study how the location-aware selection of the modulation schemes for sensors can affect their energy efficiency. Furthermore, we show how the energy in the network can be distributed more evenly by proper selection of the modulation schemes for different sensors.

Crosstalk-affected delay analysis in nanometer technologies

Abstract: This article presents a detailed analysis of the crosstalk-affected delay of coupled interconnects considering process variations. We utilise a distributed RC-π model of the interconnections to accurately model process variations. In particular, we perform a detailed investigation of various crosstalk scenarios and study the impact of different parameters on crosstalk delay. Although accounting for the effect of correlations among parameters of the neighbouring wire segments, statistical properties of the crosstalk-affected propagation delays are characterised and discussed. Monte Carlo-based simulations using Spice demonstrate the effectiveness of the proposed approach in accurately modeling the correlation-aware process variations and their impact on interconnect delay in the presence of crosstalk.

A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops

Abstract: This paper presents a novel technique to minimize the total power consumption of a synchronous linear pipeline circuit by exploiting extra slacks available in some stages of the pipeline. The key idea is to utilize soft-edge flip-flops to enable time borrowing between stages of a linear pipeline in order to provide the timing-critical stages with more time to complete their computations. Time borrowing, in conjunction with keeping the clock frequency unchanged, gives rise to a positive timing slack in each pipeline stage. The slack is subsequently utilized to minimize the circuit power consumption by reducing the supply voltage level. We formulate and solve the problem of optimally selecting the transparency window of the soft-edge flip-flops and choosing the minimum supply voltage level for the pipeline circuit as a quadratic program, thereby minimizing the power consumption of the linear pipeline circuit under a clock frequency constraint. Experimental results prove the efficacy of the problem formulation and solution technique.

Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing

Abstract: In this paper, we present a technique to optimize the energy-delay product of a synchronous linear pipeline circuit with dynamic error detection and correction capability running. The technique dynamically adjusts the supply voltage level and clock frequency of the design by exploiting slacks that are present in various stages of the pipeline. The key enabler is the utilization of soft-edge flip-flops to allow time borrowing between consecutive stages of the pipeline in order to provide the timing-critical stages with more time to complete their computations resulting in lower error probability. This raises the effective throughput of the pipeline for a fixed energy consumption level, or alternatively, lowers the energy consumption for the same effective throughput. We formulate the problem of optimally selecting the transparency window sizes of the soft-edge flip-flops and the frequency level of the pipeline circuit at different voltage levels so as to optimize the energy cost of the achieved throughput. Experimental results show the efficacy of the problem formulation and solution technique.

Resilient dynamic power management under uncertainty

Abstract: With the increasing levels of variability and randomness in the characteristics and behavior of manufactured nanoscale structures and devices, achieving performance optimization under process, voltage, and temperature (PVT) variations as well as current, voltage, and thermal (CVT) stress has become a daunting, yet vital, task. In this paper, we present a stochastic dynamic power management (DPM) framework to improve the accuracy of decision making under probabilistic conditions induced by PVT variations and/or stress. More precisely, we propose a resilient power management technique that guarantees to select an optimal policy under sources of uncertainty. A key characteristic of the proposed technique is that the effects of uncertainties due to variability and stress are captured by stochastic processes which control a self- improving power manager. Simulation results with a 65 nm processor design show that, compared to the worst-case PVT conditions, the proposed DPM technique ensures energy efficiency, while reducing the uncertain behaviors of the system.

Characterization and design of sequential circuit elements to combat soft error

Abstract: This paper performs analysis and design of latches and flip-flops while considering the effect of event upsets caused by energetic particle hits. First it is shown that the conventional analysis of this effect in sequential circuit elements (SCEs) tends to underestimate the threat posed by such events. More precisely, there exists a timing window close to the triggering edge of the clock during which a SCE is more vulnerable to the particle hit. This phenomenon has been ignored by previous work, resulting in false negatives. Next the paper explains how to size transistors of a familiar SCE i.e., a clocked CMOS latch, to make it more robust to such events. Experimental results to validate the characterization and transistor sizing steps are provided and discussed.

Wavelet-based dynamic power management for nonstationary service requests

Abstract: In this article, a wavelet-based dynamic power management policy (WBDPM) is proposed. In this approach, the workload source (service requester) is modeled by a nonstationary time series which, in turn, represented by a nondecimated Haar wavelet as its basis. The proposed approach is robust and has the ability to minimize energy dissipation under different performance constraints. To assess the accuracy of the model, the algorithm was implemented for data extracted from the hard disks of computers. Prediction results of this approach for the case of a nonstationary service requester exhibit accuracies of more than 95p.

Heterogeneous modulation for trading-off energy balancing with bandwidth efficiency in hierarchical sensor networks

Abstract: With power efficiency and lifetime awareness becoming critical design concerns in wireless sensor networks (WSN), it has become essential to exploit the physical layer characteristics at the system deployment stage This paper focuses on how certain physical layer attributes can affect both the lifetime and the end-to-end delay in a hierarchical WSN We present a heterogeneous modulation scheme and report its impact on the spatial distribution of energy dissipation and the resulting network lifetime Moreover, we study how this heterogeneous modulation scheme affects the end-to-end delay due to inherent trade-offs in power efficiency and bandwidth efficiency of the different modulation schemes

Introduction to special issue on demonstrable software systems and hardware platforms

Abstract: This special issue of the ACM Transactions on Design Automation of Electronic Systems (TODAES) contains 9 papers that were presented at the SIGDA/DAC University Booth during the 43rd Design Automation Conference (DAC) in San Francisco. Since 1987, the SIGDA/DAC University Booth (UBooth) program has been providing an excellent opportunity to the academic community to demonstrate their design techniques and tools, large-scale hardware or software projects, and educational material. Many students and faculty have benefited from the UBooth program over the last few years. At the same time, this program has made the DAC event a more interesting and learning experience for many DAC attendees. To highlight some of the work that is showcased as part of the UBooth program, the SIGDA Advisory Board in consultation with the TODAES Editor-in-Chief, Professor Nikil Dutt, has decided to include the “best” of the UBooth presentations at the 2006 DAC as peer-reviewed articles in TODAES, hence, this special issue was born. As announced in the call for participation, the focus of the special issue is on the research work that is dedicated to developing prototype software systems and/or experimental hardware platforms that offer a significant innovation in tackling key Electronic Design Automation (EDA) problems. To ensure the quality of the contributions, we also required that they contain both practical aspects of the software tool or hardware platform development as well as new and substantive algorithmic and/or theoretical enhancements to the state-of-the-art. Preference was given to the manuscripts which had accompanying technical or design contest papers at the 43rd DAC. System-level modeling, simulation, and synthesis using electronic design automation (EDA) tools are key steps in designing communication and signal processing systems. This special issue includes four articles on the system-level EDA. In the first article entitled “Efficient Simulation of Critical Synchronous Dataflow Graphs”, Hsu et al. present a novel simulation-oriented scheduler (SOS) that integrates several techniques for graph decomposition and synchronous dataflow (SDF) scheduling to provide joint minimization of time and memory requirements for simulating critical SDF graphs. The authors have implemented SOS in the Advanced Design System from Agilent Technologies and obtained large improvements in simulating large-scale wireless communication systems. Herrera and Villar in their article,“A Framework for Heterogeneous Specification and Design of Electronic Embedded Systems in SystemC”, describe a methodology that enables heterogeneous specification of complex, electronic systems in SystemC, supporting the integration of components under

Crosstalk-Affected Propagation Delay in Nanometer Technologies

Abstract: This paper presents a detailed analysis of the crosstalk-affected delay of coupled interconnects considering process variations. We utilize a distributed RC- model of the interconnections to accurately model process variations. In particular, we perform a detailed investigation of various crosstalk scenarios and study the impact of different parameters on crosstalk delay. While accounting for the effect of correlations among parameters of the neighboring wire segments, statistical properties of the crosstalk-affected propagation delays are characterized and discussed. Monte Carlo-based simulations using Spice demonstrate the effectiveness of the proposed approach in accurately modeling the correlation-aware process variations and their impact on interconnect delay in the presence of crosstalk.

In-order pulsed charge recycling in off-chip data buses

Abstract: This paper presents in-order pulsed charge recycling to reduce energy consumption in an off-chip data bus. The proposed technique performs charge recycling by employing three different steps. At the beginning of an off-chip data bus transaction, i) connect all bus lines that are expected to fall to a common node, ii) connect, one at a time and for a fixed period of time, each of bus lines that are expected to rise to the same common node to enable charge recycling, and finally, iii) resume regular data bus transaction by enabling the tri-state buffers to complete the remaining charging (discharging) of the rising (falling) bus lines. Experimental results in Hspice show that the proposed technique achieves 17.4% average energy savings in a 32 bit-wide data bus implemented in a 0.13¼m technology with a 1.8V supply voltage.