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Showing papers by "Massoud Pedram published in 2011"


Proceedings ArticleDOI
04 Jul 2011
TL;DR: An upper bound on the total profit is provided and an algorithm based on force-directed search is proposed to solve the resource allocation problem for multi-tier applications in the cloud computing.
Abstract: With increasing demand for computing and memory, distributed computing systems have attracted a lot of attention. Resource allocation is one of the most important challenges in the distributed systems specially when the clients have Service Level Agreements (SLAs) and the total profit in the system depends on how the system can meet these SLAs. In this paper, an SLA-based resource allocation problem for multi-tier applications in the cloud computing is considered. An upper bound on the total profit is provided and an algorithm based on force-directed search is proposed to solve the problem. The processing, memory requirement, and communication resources are considered as three dimensions in which optimization is performed. Simulation results demonstrate the effectiveness of the proposed heuristic algorithm.

233 citations


Proceedings ArticleDOI
14 Mar 2011
TL;DR: The constant-current charger isolates the battery from supercapacitor to improve the end-to-end efficiency for energy from the battery to the load while accounting for the rate capacity effect of Li-ion batteries and the conversion efficiencies of the converters.
Abstract: Modern batteries (e.g., Li-ion batteries) provide high discharge efficiency, but the rate capacity effect in these batteries drastically decreases the discharge efficiency as the load current increases. Electric double layer capacitors, or simply supercapacitors, have extremely low internal resistance, and a battery-supercapacitor hybrid may mitigate the rate capacity effect for high pulsed discharging current. However, a hybrid architecture comprising a simple parallel connection does not perform well when the supercapacitor capacity is small, which is a typical situation because of the low energy density and high cost of supercapacitors. This paper presents a new battery-supercapacitor hybrid system that employs a constant-current charger. The constant-current charger isolates the battery from supercapacitor to improve the end-to-end efficiency for energy from the battery to the load while accounting for the rate capacity effect of Li-ion batteries and the conversion efficiencies of the converters.

105 citations


Proceedings ArticleDOI
05 Jun 2011
TL;DR: This paper introduces the first OLED power saving technique that does not result in a significant degradation in the color and luminance values of the displayed image, based on dynamic (driving) voltage scaling (DVS) of the OLED panel.
Abstract: Unlike liquid crystal display (LCD) panels that require high-intensity backlight, organic LED (OLED) display panels naturally consume low power and provide high image quality thanks to their self-illuminating characteristic. In spite of this fact, the OLED display panel is still the dominant power consumer in battery-operated devices. As a result, there have been many attempts to reduce the OLED power consumption. Since power consumption of any pixel of the OLED display depends on the color that it displays, previous power saving methods change the pixel color subject to a tolerance level on the color distortion specified by the users. In practice, the OLED power saving techniques cannot be used on common user applications such as photo viewers and movie players. This paper introduces the first OLED power saving technique that does not result in a significant degradation in the color and luminance values of the displayed image. The proposed technique is based on dynamic (driving) voltage scaling (DVS) of the OLED panel. Although the proposed DVS technique may degrade luminance of the panel, the panel luminance can be restored with appropriate image compensation. Consequently, power is saved on the OLED display panel with only minor changes in the color and luminance of the image. This technique is similar to dynamic backlight scaling of LCDs, but is based on the unique characteristics of the OLED drivers. The proposed method saves wasted power in the driver transistor and the internal resistance with an amplitude modulation driver, and in the internal resistance with a pulse width modulation driver, respectively. Experimental results show that the proposed OLED DVS with image compensation technique saves up to 52.5% of the OLED power while keeping the same human-perceived image quality for the Lena image.

95 citations


Proceedings ArticleDOI
20 Jun 2011
TL;DR: Simulation results demonstrate that the proposed heuristic algorithm is robust (produces high quality solutions independent of the initial solution provided) and produces solutions very close to the "optimum" (best solution found by Monte Carlo simulation).
Abstract: With increasing demand for high performance computing and data storage, distributed computing systems have attracted a lot of attention. Resource allocation is one of the most important challenges in the distributed systems specially when the clients have some Service Level Agreements (SLAs) and the total profit in the system depends on how the system can meet these SLAs. In this paper, an SLA-based resource allocation problem for cloud computing is considered and a distributed solution to this problem is presented. The processing, data storage, and communication resources are considered as three dimensions in which optimizations are performed. Simulation results demonstrate that the proposed heuristic algorithm is robust (produces high quality solutions independent of the initial solution provided) and produces solutions very close to the "optimum" (best solution found by Monte Carlo simulation).

84 citations


Proceedings ArticleDOI
15 Dec 2011
TL;DR: Task scheduling policies that help consumers minimize their electrical energy cost by setting the time of use (TOU) of energy in the facility and a rank-based and force directed-based heuristic are presented to efficiently solve the problems.
Abstract: Demand response is an important part of the smart grid technologies. This is a particularly interesting problem with the availability of dynamic energy pricing models. Electricity consumers are encouraged to consume electricity more prudently in order to minimize their electric bill, which is in turn calculated based on dynamic energy prices. In this paper, task scheduling policies that help consumers minimize their electrical energy cost by setting the time of use (TOU) of energy in the facility. Moreover, the utility companies can reasonably expect that their customers reduce their consumption at critical times in response to higher energy prices during those times. These policies target two different scenarios: (i) scheduling with a TOU-dependent energy pricing function subject to a constraint on total power consumption; and (ii) scheduling with a TOU and total power consumption-dependent pricing function for electricity consumption. Exact solutions (based on Branch and Bound) are presented for these task scheduling problems. In addition, a rank-based heuristic and a force directed-based heuristic are presented to efficiently solve the aforesaid problems. The proposed heuristic solutions are demonstrated to have very high quality and competitive performance compared to the exact solutions. Moreover, ability of demand shaping utilizing the aforementioned pricing schemes is demonstrated by the simulation results.

77 citations


Proceedings ArticleDOI
05 Jun 2011
TL;DR: This paper presents an online adaptive DPM technique based on model-free reinforcement learning (RL), which is commonly used to control stochastic dynamical systems, and employs temporal difference learning for semi-Markov decision process (SMDP) for the model- free RL.
Abstract: To cope with the variations and uncertainties that emanate from hardware and application characteristics, dynamic power management (DPM) frameworks must be able to learn about the system inputs and environment and adjust the power management policy on the fly. In this paper we present an online adaptive DPM technique based on model-free reinforcement learning (RL), which is commonly used to control stochastic dynamical systems. In particular, we employ temporal difference learning for semi-Markov decision process (SMDP) for the model-free RL. In addition a novel workload predictor based on an online Bayes classifier is presented to provide effective estimates of the workload states for the RL algorithm. In this DPM framework, power and latency tradeoffs can be precisely controlled based on a user-defined parameter. Experiments show that amount of average power saving (without any increase in the latency) is up to 16.7% compared to a reference expert-based approach. Alternatively, the per-request latency reduction without any power consumption increase is up to 28.6% compared to the expert-based approach.

62 citations


Proceedings ArticleDOI
01 Aug 2011
TL;DR: This paper proposes an HEES system that consists of two or more heterogeneous EES elements, thereby realizing the advantages of each EES element while hiding their weaknesses, and provides a systematic solution for a single source and single destination charge migration.
Abstract: Electrical energy is high-quality form of energy, and thus it is beneficial to store the excessive electric energy in the electrical energy storage (EES) rather than converting into a different type of energy. Like memory devices, no single type of EES element can fulfill all the desirable requirements. Despite active research on the new EES technologies, it is not likely to have an ultimate high-efficiency, high-power/energy capacity, low-cost, and long-cycle life EES element in the near future. We propose an HEES system that consists of two or more heterogeneous EES elements, thereby realizing the advantages of each EES element while hiding their weaknesses. The HEES management problems can be broken into charge allocation into different banks of EES elements, charge replacement (i.e., discharge) from different banks of EES elements, and charge migration from one bank to another bank of EES elements. In spite of the optimal charge allocation and replacement, charge migration is mandatory to leverage the EES system efficiency. This paper is the first paper that formally describes the charge migration efficiency and its optimization. We first define the charge migration architecture and the corresponding charge migration problem. We provide a systematic solution for a single source and single destination charge migration considering the efficiency of the charger and power converter, the rate capacity effect of the storage element, the terminal voltage variation of the storage element as a function of the state of charge (SoC), and so on. Experimental results for an HEES system comprising of banks of batteries and supercapacitors demonstrate a migration efficiency improvement up to 51.3%, for supercapacitor to battery and supercapacitor to supercapacitor charge migration.

61 citations


Proceedings ArticleDOI
07 Nov 2011
TL;DR: The first paper that presents an EES bank reconfiguration architecture aiming at cycle efficiency and capacity utilization enhancement is presented, a formal definition of balanced configurations and a general reconfigurable architecture for a HEES system are provided, and key properties of the balanced reconfigurations are analyzed.
Abstract: Compared with the conventional homogeneous electrical energy storage (EES) systems, hybrid electrical energy storage (HEES) systems provide high output power and energy density as well as high power conversion efficiency and low self-discharge at a low capital cost. Cycle efficiency of a HEES system (which is defined as the ratio of energy which is delivered by the HEES system to the load device to energy which is supplied by the power source to the HEES system) is one of the most important factors in determining the overall operational cost of the system. Therefore, EES banks within the HEES system should be prudently designed in order to maximize the overall cycle efficiency. However, the cycle efficiency is not only dependent on the EES element type, but also the dynamic conditions such as charge and discharge rates and energy efficiency of peripheral power circuitries. Also, due to the practical limitations of the power conversion circuitry, the specified capacity of the EES bank cannot be fully utilized, which in turn results in over-provisioning and thus additional capital expenditure for a HEES system with a specified level of service. This is the first paper that presents an EES bank reconfiguration architecture aiming at cycle efficiency and capacity utilization enhancement. We first provide a formal definition of balanced configurations and provide a general reconfigurable architecture for a HEES system, analyze key properties of the balanced reconfiguration, and propose a dynamic reconfiguration algorithm for optimal, online adaptation of the HEES system configuration to the characteristics of the power sources and the load devices as well as internal states of the EES banks. Experimental results demonstrate an overall cycle efficiency improvement of by up to 108% for a DC power demand profile, and pulse duty cycle improvement of by up to 127% for high-current pulsed power profile. We also present analysis results for capacity utilization improvement for a reconfigurable EES bank.

56 citations


Journal ArticleDOI
TL;DR: An adaptive method to perform dynamic voltage and frequency scheduling (DVFS) for minimizing the energy consumption of microprocessor chips is presented and demonstrates considerable power savings and fewer frequency updates compared to DVFS systems based on fixed update intervals.
Abstract: An adaptive method to perform dynamic voltage and frequency scheduling (DVFS) for minimizing the energy consumption of microprocessor chips is presented. Instead of using a fixed update interval, the proposed DVFS system makes use of adaptive update intervals for optimal frequency and voltage scheduling. The optimization enables the system to rapidly track the workload changes so as to meet soft real-time deadlines. The technique, which can be realized with very simple hardware, is completely transparent to the application. The results of applying the method to some real application workloads demonstrate considerable power savings and fewer frequency updates compared to DVFS systems based on fixed update intervals.

44 citations


Proceedings ArticleDOI
14 Mar 2011
TL;DR: A variety of methods for providing analytical models for power and delay to be used in the optimization algorithms and a class of robust and scalable methods for solving multi-objective optimization problems (MOP) in a digital circuit is presented.
Abstract: The EDA design flows must be retooled to cope with the rapid increase in the number of operational modes and process corners for a VLSI circuit, which in turn results in different and sometimes conflicting design goals and requirements. Single-objective solutions to various design optimization problems, ranging from sizing and fanout optimization to technology mapping and cell placement, must hence be augmented to deal with this changing landscape. This paper starts off by presenting a variety of methods for providing analytical models for power and delay to be used in the optimization algorithms. The modeling includes non-convex and convex functional forms. Next, a class of robust and scalable methods for solving multi-objective optimization problems (MOP) in a digital circuit is presented. We present the results of a multi-objective (i.e., power dissipation and delay) gate (transistor) sizing optimization algorithm to demonstrate the effectiveness of our method. We set up the problem as a simultaneous, multi-objective optimization problem and solve it by using the Weighted Sum and Compromise Programming methods. After comparing these two methods, we present the Satisficing Trade-off Method (STOM) to find the most desirable operating point of a circuit.

35 citations


Proceedings ArticleDOI
09 Oct 2011
TL;DR: This paper is the first paper to formally describe the charge allocation problem and provide a systematic solution method aiming at the maximum charge allocation efficiency, which performing proper distribution of the incoming power to selected destination banks.
Abstract: Hybrid electrical energy storage (HEES) systems, composed of multiple banks of heterogeneous electrical energy storage (EES) elements with their unique strengths and weaknesses, have been introduced to efficiently store and retrieve electrical energy while attaining performance metrics that are close to their respective best values across their constituent EES elements. This paper is the first paper to formally describe the charge allocation problem and provide a systematic solution method aiming at the maximum charge allocation efficiency, which performing proper distribution of the incoming power to selected destination banks. We introduce a generalized HEES architecture and build the corresponding electrical circuit models of the chargers and banks. We formulate a mixed integer nonlinear optimization problem, where the objective function is the global charge allocation efficiency, and the constraints are energy conservations, with careful consideration of the conversion power loss in the chargers, rate capacity effect and self-discharge of the EES elements, charge transfer losses, and so on. We present a rigorous algorithm to achieve a near-optimal global charge allocation efficiency for long-term charge allocation process (i.e., tens of hours.) Experimental results based on a photovoltaic cell array as the incoming power source and a HEES system comprised on batteries and supercapacitors demonstrate a significant gain in charge allocation efficiency for the proposed algorithm.

Proceedings ArticleDOI
01 Aug 2011
TL;DR: This paper provides an accurate parameter characterization methodology with nonlinear curve fitting to minimize the model discrepancy over the entire operating range and Experimental results show significant improvement in the emulation accuracy.
Abstract: Photovoltaic (PV) cells are promising endurable renewable power sources that do not include mechanical components, which are subject to wear and tear. However, actual development of a solar-powered system requires elaborated design processes to find the best setup including location determination and development of a maximum power point tracking method, which requires numerous on-site experiments. This paper introduces a versatile PV module emulation system, which can cover a range of different PV modules and environmental conditions. We provide an accurate parameter characterization methodology with nonlinear curve fitting to minimize the model discrepancy over the entire operating range. The proposed PV module emulation system includes a pilot PV cell, temperature sensors, an accelerometer, and a magnetic sensor, and provides features for the PV module characterization and emulation modes. Experimental results show significant improvement in the emulation accuracy, which comes from the advanced PV module characterization method as well as high-precision hardware and control.

Journal ArticleDOI
TL;DR: A highly accurate CSM for combinational logic cells is presented, followed by models for common sequential cells, including latches and master slave flip-flops, which can be used for accurate noise and delay analysis in CMOS VLSI circuits.
Abstract: A current source model (CSM) for CMOS logic cells is presented, which can be used for accurate noise and delay analysis in CMOS VLSI circuits CS modeling is broadly considered as the method of choice for modern static timing and noise analysis tools Unfortunately, the existing CSMs are only applicable to combinational logic cells In addition to multistage logic nature of the sequential cells, the main difficulty in developing a CSM for these cells is the presence of feedback loops This paper begins by presenting a highly accurate CSM for combinational logic cells, followed by models for common sequential cells, including latches and master slave flip-flops The proposed model addresses these problems by characterizing the cell with suitable nonlinear CSs and capacitive components Given the input and clock voltage waveforms of arbitrary shapes, our new model can accurately compute the output voltage waveform of the sequential cell Experimental results demonstrate close-to-SPICE waveforms with three orders of magnitude speedup

Proceedings ArticleDOI
14 Mar 2011
TL;DR: The delay Probability Density Function (PDF) of the CIs is used in identification and selection phases of the CI extension considering process variations to bridge the gap between the high level custom instruction extension and chip fabrication in nanotechnologies.
Abstract: In this paper, we propose a technique for custom instruction (CI) extension considering process variations. It bridges the gap between the high level custom instruction extension and chip fabrication in nanotechnologies. In the proposed method, instead of using the conventional static timing analysis (STA), statistical static timing analysis (SSTA) which in turn results in a probabilistic approach to identifying and selecting different parts of the CI extension is utilized. More precisely, we use the delay Probability Density Function (PDF) of the CIs in identification and selection phases of the CI extension. In the identification phase, the delay of each CI is modeled by PDF whereas the performance yield is added as a constraint. Additionally, in the selection phase, the merit function of the conventional approaches is modified to increase the performance gain of the selected CIs at the price of slightly sacrificing the design yield. Also, to make the approach computationally more efficient, we propose a method for reducing the modeling time of the PDF of the CIs by reducing the number of candidate CIs before extracting the PDF.

Journal ArticleDOI
TL;DR: This paper uses soft-edge flip-flops to allow time borrowing among consecutive stages of the pipeline in order to provide the timing-critical stages with more time and trade this timing slack for power saving, and forms the problem of power-delay optimal soft linear pipeline design.
Abstract: In this paper, we present and solve the problem of power-delay optimal soft linear pipeline design. The key idea is to use soft-edge flip-flops to allow time borrowing among consecutive stages of the pipeline in order to provide the timing-critical stages with more time and trade this timing slack for power saving. We formulate the problem of optimally designing the soft-edge flip-flops and setting the clock frequency and supply voltage so as to minimize the power-delay product of a linear pipeline under different scenarios using both deterministic and statistical static delay models. In our first problem formulation, timing violations are avoided by respecting deterministic worst case path delay bounds. Next, the same problem is formulated for a scenario where stage delays are assumed to be random variables, and we minimize the power-delay product while keeping the probability of timing violations bounded. The soft-edge flip flops are equipped with dynamic error detection (and correction) circuitry to detect and fix the errors that might arise from over-clocking. Although the system is capable of recovering from error, there is a tradeoff between performance and power saving, which is exploited to further minimize the power-delay product of the pipeline in our third formulation. Experimental results demonstrate the efficacy of our proposed algorithms for solving each of the aforesaid problems.

Proceedings ArticleDOI
05 Jun 2011
TL;DR: This paper sets up a novel transformation technique to manipulate the constraints of the optimization problem to be solved by using conjugate gradient (CG) method and shows that by doing this optimization, it can reduce the leakage power consumption by 34% on average in comparison with no power optimization after sign-off.
Abstract: With the scaling down of the CMOS technologies, leakage power is becoming an increasingly important issue in IC design. There is a trade-off between subthreshold leakage power consumption and clock frequency in the circuit; i.e., for higher performance, leakage power consumption must be sacrificed and vice versa. Meanwhile, timing analysis during synthesis and physical design is pessimistic, which means there are some slacks available to be traded for leakage power minimization. This power minimization can be done after the sign-off which is more accurate and realistic than if it is done before the sign-off. The available slack can be traded for leakage power minimization by footprint-based cell swapping and threshold voltage assignment. In this paper, we introduce our post sign-off leakage power optimization problem as a nonlinear mathematical program and solve it by using conjugate gradient (CG) method. We set up a novel transformation technique to manipulate the constraints of the optimization problem to be solved by CG. We show that by doing this optimization we can reduce the leakage power consumption by 34% on average in comparison with no power optimization after sign-off. All experiments are done on the real industrial designs.

01 Jan 2011
TL;DR: The special issue is intended to delineate the state-of-the-art and challenges facing the PE industry, as well as, to present the current activities, solutions, and future work of researchers, both from academia and industry, in this emerging field.
Abstract: The purpose of this special issue is to engage the engineering and scientific communities, particularly the IEEE, in the emerging ‘Organic Electronics’, also commonly known as ‘Printed Electronics’ (PE). The special issue is intended to delineate the state-of-the-art and challenges facing the PE industry, as well as, to present the current activities, solutions, and future work of researchers, both from academia and industry, in this emerging field. Another purpose is to connect the different disciplines embodied in PE, with emphasis on their implications to circuit design – from a circuits and systems perspective. Broadly, PE encompasses five supply chains: (i) Materials; (ii) Processing Equipment/Platforms; (iii) Circuits/Power Source/Display/Memory/Sensors; (iv) System Integration; and (v) Test and Verification. The scope of this special issue virtually covers all these chains with focus on how they, individually or collectively, affect the printed elements and hence the ensuing circuits and systems. Of specific interest, the scope includes the co-design of the different chains with the third chain (Circuits/Power Source/Display/Memory/Sensors); particularly how innovative circuits and systems design may be able to circumvent or at least mitigate the formidable challenges and shortcomings of PE. Both PE-only (fully-printed) and ‘Hybrid Electronics’ (embodying a heterogeneous integration of conventional silicon transistors with printed circuit elements) on flexible substrate, such as PET plastic films, are within the scope of this special issue. However, there is emphasis for full realizations on flexible substrates (PE-only) as this significantly broadens the application space of PE, for instance, as a key technological enabler for the Internet-of-Things. Put simply, the overall scope encompasses all aspects of the multi-disciplinary PE with emphasis in a circuits and systems perspective and includes: a. Provide prevailing and open problems of PE to the engineering and scientific communities, including the circuits and systems and solid-state design communities;

Proceedings ArticleDOI
14 Mar 2011
TL;DR: This paper adopts a Markovian Decision Process based approach to CMP power management problem, and models the underlying variability and uncertainty of parameters in system level as a partially observable MDP, and finds the optimal policy that stochastically minimizes energy per request.
Abstract: With the increasing levels of variability in the characteristics of VLSI circuits and continued uncertainty in the operating conditions of processors, achieving predictable power efficiency and high performance in the electronic systems has become a daunting, yet vital, task. This paper tackles the problem of system-level dynamic power management (DPM) in the state-of-the-art chip multiprocessor (CMP) architectures that are manufactured in nanoscale CMOS technologies with large process variations or are operated under widely varying environmental conditions over their lifetime. We adopt a Markovian Decision Process based approach to CMP power management problem. The proposed technique models the underlying variability and uncertainty of parameters in system level as a partially observable MDP, and finds the optimal policy that stochastically minimizes energy per request. Experimental results demonstrate the high efficacy of the proposed power management framework.

Proceedings ArticleDOI
27 Mar 2011
TL;DR: A number of best practices and methods for improving the power-performance efficiency of VLSI circuits and systems are presented, which range from dynamic power management to design of power-aware circuits, and from power/clock gating to leakage power minimization.
Abstract: Digital information management is the key enabler for the unparalleled rise in productivity and efficiency gains experienced by the world economies. Computing and information processing systems are important elements of the world's digital infrastructure by providing ever-present and ever-increasing general purpose and data-driven processing and storage capabilities for both wired and mobile users. As such, they are also significant drivers of economic growth and social change. However, continued expansion of computing and information processing systems is now hindered by their unsustainable and rising power needs, with associated electrical energy costs and peak power draw requirements. Moreover governments, people, and corporations are becoming increasingly concerned about the environmental impact of these systems i.e., their carbon footprint. Separately from all this, with the increasing levels of variability in the characteristics of nanoscale CMOS devices and on-chip interconnects and continued uncertainty in the operating conditions of VLSI circuits, achieving power efficiency and high performance in computing and information processing systems under process, voltage, and temperature variations as well as interconnect wear-out and device aging has become a daunting, yet vital, task.It is against this backdrop of rising power demands and energy costs as well as increased device- and circuit-level variability and aging effects that I present a number of best practices and methods for improving the power-performance efficiency of VLSI circuits and systems. The reviewed techniques range from dynamic power management to design of power-aware circuits, and from power/clock gating to leakage power minimization. A key issue to be addressed is how to deal with process and environment-induced variability of circuit parameters through statistical modeling and robust optimization and how to manage uncertainty about the workload and input data characteristics through observations and closed feedback loop control.