There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

Machine Learning is the study of methods for programming computers to learn. Computers are applied to a wide range of tasks, and for most of these it is relatively easy for programmers to design and implement the necessary software. However, there are many tasks for which this is difficult or impossible. These can be divided into four general categories. First, there are problems for which there exist no human experts. For example, in modern automated manufacturing facilities, there is a need to predict machine failures before they occur by analyzing sensor readings. Because the machines are new, there are no human experts who can be interviewed by a programmer to provide the knowledge necessary to build a computer system. A machine learning system can study recorded data and subsequent machine failures and learn prediction rules. Second, there are problems where human experts exist, but where they are unable to explain their expertise. This is the case in many perceptual tasks, such as speech recognition, hand-writing recognition, and natural language understanding. Virtually all humans exhibit expert-level abilities on these tasks, but none of them can describe the detailed steps that they follow as they perform them. Fortunately, humans can provide machines with examples of the inputs and correct outputs for these tasks, so machine learning algorithms can learn to map the inputs to the outputs. Third, there are problems where phenomena are changing rapidly. In finance, for example, people would like to predict the future behavior of the stock market, of consumer purchases, or of exchange rates. These behaviors change frequently, so that even if a programmer could construct a good predictive computer program, it would need to be rewritten frequently. A learning program can relieve the programmer of this burden by constantly modifying and tuning a set of learned prediction rules. Fourth, there are applications that need to be customized for each computer user separately. Consider, for example, a program to filter unwanted electronic mail messages. Different users will need different filters. It is unreasonable to expect each user to program his or her own rules, and it is infeasible to provide every user with a software engineer to keep the rules up-to-date. A machine learning system can learn which mail messages the user rejects and maintain the filtering rules automatically. Machine learning addresses many of the same research questions as the fields of statistics, data mining, and psychology, but with differences of emphasis. Statistics focuses on understanding the phenomena that have generated the data, often with the goal of testing different hypotheses about those phenomena. Data mining seeks to find patterns in the data that are understandable by people. Psychological studies of human learning aspire to understand the mechanisms underlying the various learning behaviors exhibited by people (concept learning, skill acquisition, strategy change, etc.).

Machine learning

Probability Distributions.- Linear Models for Regression.- Linear Models for Classification.- Neural Networks.- Kernel Methods.- Sparse Kernel Machines.- Graphical Models.- Mixture Models and EM.- Approximate Inference.- Sampling Methods.- Continuous Latent Variables.- Sequential Data.- Combining Models.

Pattern Recognition and Machine Learning

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Convex Analysisの二,三の進展について

This paper reports a runtime accuracy reconfigurable implementation of an energy efficient deep learning accelerator. The accelerator utilizes the voltage overscaling (VOS) technique, which provides adjustment of the approximation level of the hardware components while improving lifetime/reliability of the accelerator. The technique is targeted at computing units where the applied voltage is adjusted at runtime based on the minimum required accuracy. The implementation of the network is performed using NVDLA which is an open-source Convolutional Neural Network (CNN) accelerator. The approximation is applied to the accelerator multiply-and-accumulate (MAC) array employed for the required network computations. To control the accuracy degradation of the approximate accelerator (called X-NVDLA), the reduced voltage is applied only to least significant bits (LSBs) of the MAC array. To assess the efficacy of the proposed energy efficient accelerator, the energy-accuracy characteristics of X-NVDLA when running LeNet-5 and ResNet-50 networks with 8-bit (integer) precision are investigated. The study includes energy improvement versus accuracy degradation as a function of overscaled voltages and number of approximate LSBs using a 15nm FinFET technology.

X-NVDLA: Runtime Accuracy Configurable NVDLA based on Employing Voltage Overscaling Approach

This paper proposes a robust and energy-efficient hybrid TFET-FinFET 6T SRAM cell which takes advantage of the higher ON/OFF current ratio of TFETs compared to that of FinFETs to reliably hold and access data at ultra-low supply voltages. More precisely, in the proposed hybrid cell, to achieve low static currents along with high noise margins, TFETs are used for cross-coupled inverters, and to speed up the access time, high-performance FinFETs are utilized for access transistors. The paper also presents a dual-V t 6T SRAM, in which low-power (high-V t ) and high-performance (low-V t ) FinFETs are used for cross-coupled inverters and access transistors, respectively. For both SRAM cells, the V dd boost read-assist technique is employed to improve the read stability. Characteristics of both SRAMs are analyzed using HSPICE simulations for technologies with the gate length of 20 nm for a 128\times 128 SRAM array. Simulation results reveal that the lowest operating V dd for the dual-V t cell is 225 mV, whereas that of the hybrid cell is 125 mV. Moreover, to further decrease the access delay of the hybrid cell for 125 mV ≤ V dd ≤ 225 mV, negative Gnd read-assist technique and a boosted voltage for the row decoder are used. Finally, the paper presents a 125mV 2ns-access-time 16Kb SRAM array based on the proposed hybrid TFET-FinFET SRAM cell.

A 125mV 2ns-access-time 16Kb SRAM design based on a 6T hybrid TFET-FinFET cell

Two-level logic minimization has found applications in new problems such as efficient realization of deep neural network inference. Important characteristics of these new applications are that they tend to produce very large Boolean functions (in terms of the supporting variables and/or initial sum of product representation) and have don't-care-sets that are much larger in size than the on-set and off-set sizes. Applying conventional single-threaded logic minimization heuristics to these problems becomes unwieldy. This work introduces ESPRESSO-GPU, a parallel version of ESPRESSO-II, which takes advantage of the computing capabilities of general-purpose graphics processors to achieve a huge speedup compared to existing serial implementations. Simulation results show that ESPRESSO-GPU achieves an average speedup of 97x compared to ESPRESSO-II.

ESPRESSO-GPU: Blazingly Fast Two-Level Logic Minimization

This paper studies the impact of the delay degradation arising from the Negative Bias Temperature Instability (NTBI) effect on the extended instruction set architecture (ISA) and the ALU design of extensible processors. In particular, the NBTI delay degradation on the performance of extensible processors is modeled during the conventional design flow. While the results of this study show that, in some cases, the lifetime of the extensible processors is decreased, in most cases, the extended ISA is able to improve the lifetime compared to the baseline processor. Next, three different design flows are presented to lower the NBTI effect. These flows are based on reducing the stress on custom instructions (CIs) by considering the number of occurrences of the selected CIs in the data flow graph of the target application and by pruning the CIs whose NBTI-induced delay degradations are large and result in slow down of the extensible processor. Experimental results assess the effectiveness of the proposed methods.

Capturing and mitigating the NBTI effect during the design flow for extensible processors

This paper presents a synthesis methodology for ECL circuits based on a mixed voltage-current signal representation and operation defined on the voltage and current signals. The ideas presented in this paper are then demonstrated on the design of an ECL 1-bit full adder. The paper concludes by presenting an algebraic system which is suitable for current signal representation and operation on currents.

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Massoud Pedram

Papers

X-NVDLA: Runtime Accuracy Configurable NVDLA based on Employing Voltage Overscaling Approach

A 125mV 2ns-access-time 16Kb SRAM design based on a 6T hybrid TFET-FinFET cell

ESPRESSO-GPU: Blazingly Fast Two-Level Logic Minimization

Capturing and mitigating the NBTI effect during the design flow for extensible processors

A synthesis methodology for ECL circuits based on mixed voltage-current representation