Massoud Pedram

TL;DR: The proposed solution relies on a hierarchical framework, which employs core consolidation, coarse-grain dynamic voltage and frequency scaling (DVFS), and task assignment at the CMP level and fine-grain DVFS based on closed-loop feedback control at the individual core level to demonstrate the high efficacy of the proposed hierarchical PM framework.

TL;DR: Basic techniques are described, that are applicable at RT-level and below, and have proved to hold good potential for power optimisation in practical design environments.

TL;DR: In this paper, a detailed scaling analysis of the power supply distribution network voltage drop in DSM technologies is presented, and the effects of chip temperature, electromigration and interconnect technology scaling (including resistivity increase of Cu interconnects due to electron surface scattering and finite barrier thickness) are taken into consideration during this analysis.

TL;DR: A dual-mode power regulator for the PV emulation that provides accurate emulation results over the full operating range of the PV module by complementary use of the two regulators and develops a robust control method for producing an accurate I–V curve with compensation of the loss in the circuit components.

TL;DR: New designs of FPGA subcircuits for both synchronous and asynchronous operation of SFQ circuits are presented in this paper, andEstimations for the area and power consumption are much better in comparison to previous attempts at designing an SFQ specific FPGAs.