M
Massoud Pedram
Researcher at University of Southern California
Publications - 812
Citations - 25236
Massoud Pedram is an academic researcher from University of Southern California. The author has contributed to research in topics: Energy consumption & CMOS. The author has an hindex of 77, co-authored 780 publications receiving 23047 citations. Previous affiliations of Massoud Pedram include University of California, Berkeley & Syracuse University.
Papers
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Proceedings ArticleDOI
MERLIN: semi-order-independent hierarchical buffered routing tree generation using local neighborhood search
TL;DR: This method finds the best solution of the problem of performance-driven buffered routing tree generation in electronic circuits in an exponential size solution subspace in polynomial time using a novel bottom-up construction algorithm and a local neighborhood search strategy.
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Optimizing the Power-Delay Product of a Linear Pipeline by Opportunistic Time Borrowing
TL;DR: This paper uses soft-edge flip-flops to allow time borrowing among consecutive stages of the pipeline in order to provide the timing-critical stages with more time and trade this timing slack for power saving, and forms the problem of power-delay optimal soft linear pipeline design.
Proceedings ArticleDOI
Technology mapping for low leakage power and high speed with hot-carrier effect consideration
Chang-woo Kang,Massoud Pedram +1 more
TL;DR: Experimental results show that the total power Dissipation and leakage power dissipation can be reduced by up to 27% and 52% as a result of the leakage-aware technology mapping and that the circuit aging phenomenon can be reducing by upto 10.6% as an result of hot-carrier-awareTechnology mapping.
Journal ArticleDOI
An Exploration of Applying Gate-Length-Biasing Techniques to Deeply-Scaled FinFETs Operating in Multiple Voltage Regimes
TL;DR: A device-circuit cross-layer framework to utilize fine-grained gate-length biased FinFETs for circuit leakage power reduction in near- and super-threshold operation regimes is presented.
Proceedings ArticleDOI
Hierarchical dynamic power management using model-free reinforcement learning
TL;DR: An architecture for hierarchical DPM in an embedded system composed of a processor chip and connected I/O devices (which are called system components) is presented to facilitate saving in the system component power consumption, which tends to dominate the total power consumption.