M
Massoud Pedram
Researcher at University of Southern California
Publications - 812
Citations - 25236
Massoud Pedram is an academic researcher from University of Southern California. The author has contributed to research in topics: Energy consumption & CMOS. The author has an hindex of 77, co-authored 780 publications receiving 23047 citations. Previous affiliations of Massoud Pedram include University of California, Berkeley & Syracuse University.
Papers
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Journal ArticleDOI
Design and Multicorner Optimization of the Energy-Delay Product of CMOS Flip–Flops Under the Negative Bias Temperature Instability Effect
TL;DR: It is shown that the NBTI effect tightens the setup and hold timing constraints imposed on the flip-flops in the design, and a multicorner optimization technique is presented to minimize the energy-delay product of the flips under the N BTI effect.
Journal ArticleDOI
Distributing DNN training over IoT edge devices based on transfer learning
TL;DR: In this paper, an approach for distributing the deep neural network (DNN) training onto IoT edge devices is proposed, which results in protecting data privacy on the edge devices and decreasing the load on cloud servers.
Proceedings ArticleDOI
A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops
TL;DR: This paper formulate and solve the problem of optimally selecting the transparency window of the soft-edge flip-flops and choosing the minimum supply voltage level for the pipeline circuit as a quadratic program, thereby minimizing the power consumption of the linear pipeline circuit under a clock frequency constraint.
Book ChapterDOI
Advanced power estimation techniques
TL;DR: The major components of the proposed methodology are survey sampling techniques, probabilistic compaction techniques, RTL co-simulation engine, power macro-modeling, and high-level power estimation.
Proceedings ArticleDOI
NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational Logic
Mahdi Nazemi,Arash Fayyazi,Amirhossein Esmaili,Atharva Khare,Soheil Nazar Shahsavani,Massoud Pedram +5 more
TL;DR: In this article, the authors proposed a field-programmable gate array (FPGA)-based DNN accelerators for ultra-low-latency realization of these models for applications with stringent, sub-microsecond latency requirements.