A low-power high linearity CMOS Gm-C channel select filter for WLAN/WiMAX receivers in 90-nm CMOS technology is presented. To reduce power consumption a biquad cell with simple architecture is used. A simple but efficient technique is also proposed to improve the linearity of the filter without increasing its power consumption. Coarse and fine tuning techniques are used to tune the cutoff frequency of the sixth-order Butterworth low-pass filter from 8.1 MHz to 13.5 MHz suitable for WLAN and WiMAX applications. The measurement results show an in-band IIP3 of + 22 dBm, an HD3 better than - 40 dB at 470 mVP input signal amplitude, and an input referred noise of 75 nV/√Hz at a power consumption of 4.35 mW from a 1-V supply. The differential filter occupies a chip area of 0.239 mm2 excluding pads.

A CMOS 4.35-mW +22-dBm IIP3 Continuously Tunable Channel Select Filter for WLAN/WiMAX Receivers

An architectural attenuation-predistortion linearization scheme for a wide range of operational transconductance amplifiers (OTAs) is proposed and demonstrated with a transconductance-capacitor (Gm-C) filter. The linearization technique utilizes two matched OTAs to cancel output harmonics, creating a robust architecture. Compensation for process variations and frequency-dependent distortion based on Volterra series analysis is achieved by employing a delay equalization scheme with on-chip programmable resistors. An OTA design with the proposed broadband linearization method has third-order inter-modulation (IM3) distortion better than -74 dB up to 350 MHz with 0.2V?? input, 70 dB signal-to-noise ratio (SNR) in 1 MHz bandwidth, and 5.2 mW power consumption. The distortion-cancellation technique enables an IM3 improvement of up to 22 dB compared to a commensurate OTA without linearization. A proof-of-concept low-pass filter with the linearized OTAs has a measured IM3 < - 70 dB and 54.5 dB dynamic range over its 195 MHz bandwidth. The standalone OTAs and the filter were fabricated on a 0.13 ?m CMOS test chip with 1.2 V supply.

Attenuation-Predistortion Linearization of CMOS OTAs With Digital Correction of Process Variations in OTA-C Filter Applications

This paper proposes a biquad design methodology and presents a baseband low-pass filter for wireless and wireline applications with reconfigurable frequency response (Chebyshev/Inverse Chebyshev), selectable order (1st/3rd/5th), continuously tunable cutoff frequency (1-20 MHz), and adjustable power consumption (3-7.5 mW). A discrete capacitor array coarsely tunes the low-pass filter, and a novel continuous impedance multiplier (CIM) then finely tunes the filter. Resistive/capacitive networks select between the Chebyshev and inverse Chebyshev approximation types. Also, a new stability metric for biquads, minimum acceptable phase margin (MAPM), is presented and discussed in the context of filter compensation and passband ripple considerations. Experimental results yield an IIP3 of 31.3 dBm, a THD of -40 dB at 447 mVpk, diff input signal amplitude, and a DR of 71.4 dB. The filter's tunable range covers frequencies from 1 MHz to 20 MHz. In Inverse Chebyshev mode, the filter achieves a passband group delay variation less than plusmn2.5%. The design is fabricated in 0.13 mum CMOS, occupies 1.53 mm2 , and operates from a 1-V supply.

A 1-V +31 dBm IIP3, Reconfigurable, Continuously Tunable, Power-Adjustable Active-RC LPF

This paper introduces an area- and power-efficient approach for compressive recording of cortical signals used in an implantable system prior to transmission. Recent research on compressive sensing has shown promising results for sub-Nyquist sampling of sparse biological signals. Still, any large-scale implementation of this technique faces critical issues caused by the increased hardware intensity. The cost of implementing compressive sensing in a multichannel system in terms of area usage can be significantly higher than a conventional data acquisition system without compression. To tackle this issue, a new multichannel compressive sensing scheme which exploits the spatial sparsity of the signals recorded from the electrodes of the sensor array is proposed. The analysis shows that using this method, the power efficiency is preserved to a great extent while the area overhead is significantly reduced resulting in an improved power-area product. The proposed circuit architecture is implemented in a UMC 0.18 ${\mbi \mu}$ m CMOS technology. Extensive performance analysis and design optimization has been done resulting in a low-noise, compact and power-efficient implementation. The results of simulations and subsequent reconstructions show the possibility of recovering fourfold compressed intracranial EEG signals with an SNR as high as 21.8 dB, while consuming 10.5 ${\mbi \mu}$ W of power within an effective area of 250 ${\mbi \mu}$ m $\, \times \,$ 250 ${\mbi \mu}$ m per channel.

Compact Low-Power Cortical Recording Architecture for Compressive Multichannel Data Acquisition

In this paper, a 4th-order low-pass continuous-time analog filter is presented, that is implemented with the cascade of two efficient and compact biquadratic cells, realized using the Super-Source-Follower topology. The biquadratic cell uses only two capacitors and four transistors: two transistors for the signal processing and two transistors as current sources for biasing purpose. The 4th-order filter prototype has been integrated in 0.18 µm CMOS technology. For a 33 MHz cut-off frequency, the filter performs 18 dBm-IIP3 for two tones at 2 MHz and 3 MHz, with total current of 770 µA from a single 1.8 V supply voltage.

A 33 MHz 70 dB-SNR Super-Source-Follower-Based Low-Pass Analog Filter

In this paper, a "composite" source-follower is presented. Using a positive-feedback, the structure synthesizes complex poles with a single branch. This allows to realize a single-branch biquadratic cell. Moreover, due to the intrinsic feedback present in any source-follower, the proposed cell performs larger linearity for smaller Vov(=VGS-VTH). This is the opposite of other active filters and allows saving the power otherwise used to increase linearity. A fourth-order prototype satisfy typical WLAN 802.11.a/b/g baseband filter specifications has been realized in a 0.18 mum CMOS at 1.8-V supply. It achieves a 17.5-dBm IIP3 and a -40 dB HD3 for a 600-mVpp_diff input signal amplitude. A 24-muVrms noise gives a DR=79 dB, with 2.25-mA current consumption

A 4.1-mW 10-MHz Fourth-Order Source-Follower-Based Continuous-Time Filter With 79-dB DR

In this paper, a "composite" source-follower is presented. Using a positive-feedback, the structure synthesizes complex poles with a single branch. This allows to realize a single-branch biquadratic cell. Moreover, due to the intrinsic feedback present in any source-follower, the proposed cell performs larger linearity for smaller V ov (= V GS - V TH ). This is the opposite of other active filters and allows saving the power otherwise used to increase linearity. A fourth-order prototype satisfy typical WLAN 802.11-a/b/g baseband filter specifications has been realized in a 0.18 μm CMOS at 1.8-V supply. It achieves a 17.5-dBm IIP3 and a -40 dB HD3 for a 600-mV pp_diff input signal amplitude. A 24-μV rms noise gives a DR = 79 dB, with 2.25-mA current consumption.

Matteo Conta

Papers

A 4.1-mW 10-MHz Fourth-Order Source-Follower-Based Continuous-Time Filter With 79-dB DR

A 4.1-mW 10-MHz fourth-order source-follower-based continuous-time filter with 79-dB DR