Showing papers by "Matteo Sonza Reorda published in 1996"

GALLO: a genetic algorithm for floorplan area optimization

Abstract: The paper describes a Genetic Algorithm for the Floorplan Area Optimization problem. The algorithm is based on suitable techniques for solution encoding and evaluation function definition, effective cross-over and mutation operators, and heuristic operators which further improve the method's effectiveness. An adaptive approach automatically provides the optimal values for the activation probabilities of the operators. Experimental results show that the proposed method is competitive with the most effective ones as far as the CPU time requirements and the result accuracy is considered, but it also presents some advantages. It requires a limited amount of memory, it is not sensible to special structures which are critical for other methods, and has a complexity which grows linearly with the number of implementations. Finally, we demonstrate that the method is able to handle floorplans much larger (in terms of number of basic rectangles) than any benchmark previously considered in the literature.

A genetic algorithm for automatic generation of test logic for digital circuits

Abstract: Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-in Self-Test) techniques is increasingly popular, but sometimes requires efficient algorithms for the automatic generation of the logic which generates the test vectors applied to the unit under test. This paper addresses the issue of identifying a cellular automaton able to generate input patterns to detect stuck-at faults inside a finite state machine (FSM). A suitable hardware structure is first identified. A genetic algorithm is then proposed, which directly identifies a cellular automaton able to reach a very good fault coverage of the stuck-at faults. The novelty of the method consists in combining the generation of test patterns with the synthesis of a cellular automaton able to reproduce them. Experimental results are provided, which show that in most of the standard benchmark circuits the cellular automaton selected by the genetic algorithm is able to reach a fault coverage close to the maximum one. Our approach is the first attempt of exploiting evolutionary techniques for identifying the hardware for input pattern generation in BIST structures.

Circular self-test path for FSMs

Abstract: Circular self test path (CSTP) is an attractive method for automatically transforming sequential circuits generated by automatic synthesis tools into BIST structures. The authors extend this method-making it more suitable for FSMs derived from synthesized control parts-and are integrating it into an industrial design flow supporting testable synthesis. The CSTP approach provides good results in terms of test length and fault coverage in large circuits. It requires substitution of all or some of the flip-flops in the circuit with special cells and their connection to constitute a circular chain. CSTP also has application in industrial environments, and several commercial CAE environments, such as that used by AT&T, now support CSTP as an approach for automatic introduction of BIST in circuits.

On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications

Abstract: The paper describes the strategy adopted to implement on-line test procedures for a commercial microprocessor board used in an automated light-metro control system. Special care has been devoted to chose the most effective test strategy for memory elements, processors, and caches, while guaranteeing a minimum impact on the normal behavior of the whole system. Implementation of the described techniques will significantly improve the system ability to safely react to possible faults. This will be quantitatively determined in the subsequent dependability evaluation phase.

A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits

Abstract: The paper deals with the problem of Automatic Generation of Test Sequences for digital circuits. Genetic Algorithms have been successfully proposed to solve this industrially critical problem; however, they have some drawbacks, e.g., they are often unable to detect some hard to test faults, and require a careful tuning of the algorithm parameters. In this paper, we describe a new parallel version of an existing GA-based ATPG, which exploits competing sub-populations to overcome these problems. The new approach has been implemented in the PVM environment and has been evaluated on a workstation network using some of the standard benchmark circuits. The results show that it is able to significantly improve the results quality (by testing some critical faults) at the expense of increased CPU time requirements.

Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Cicuits

Abstract: The paper describes the application of a Parallel Genetic Algorithm to Automatic Test Pattern Generation (ATPG) for digital circuits Genetic Algorithms have been already proposed to solve this industrially critical problem, both on mono- and multi-processor architectures Although preliminary results are very encouraging, there are some obstacles which limit their use: in particular, GAs are often unable to detect some hard to test faults, and require a careful tuning of the algorithm parameters In this paper, we describe a new parallel version of an existing GA-based ATPG, which exploits competing sub-populations to overcome these problems The new approach has been implemented in the PVM environment and has been evaluated on a workstation network using standard benchmark circuits Preliminary results show that it is able to improve the results quality (by testing additional critical faults) at the expense of increased CPU time requirements

Self-checking and fault tolerant approaches can help BIST fault coverage: a case study

Abstract: Summary form only given. We describe the design of an FIFO component with BIST capabilities. The component is now being used in the Italtel standard library and is exploited in several industrial designs. Our main contribution is to show how the effectiveness of complex BIST design can be improved, and brought to acceptable fault coverage levels, through the coupling with more advanced test architectures developed for online testing schemes. We adopted fault tolerant schemes and self-checking components to ensure that critical circuitry is working correctly.