Showing papers by "Matteo Sonza Reorda published in 1997"

Optimizing area loss in flat glass cutting

Abstract: This paper describes GGOAL, a genetic algorithm for the minimization of glass loss in cutting large sheets into several pieces. The algorithm takes into account several industrial constraints, stemming both from the glass cutting technology and from the requirement that the optimization must run in real-time, concurrently with the cutting operation. The algorithm delivers comparable or better results than optimization procedures embedded in comprehensive commercial software systems, and is now distributed with all flat glass cutting machines sold by Bottero SpA.

Boolean Function Manipulation on a Parallel System Using BDDs

Abstract: This paper describes a distributed algorithm for Boolean function manipulation The algorithm is based on Binary Decision Diagrams (BDDs), which are one of the most commonly used data structures for representing and manipulating Boolean functions A new distributed version of a BDD data structure and a distributed implementation of the basic operator for its manipulation are presented The algorithm is suitable to work on a MIMD architecture and is based on a message passing master-slave paradigm A package has been written, which uses the PVM library and is portable on different architectures

A genetic algorithm for the computation of initialization sequences for synchronous sequential circuits

Abstract: Testing circuits which do not include a global reset signal requires either complex ATPG algorithms based on 9- or even 256-valued algebras, or some suitable method to generate initialization sequences. This paper follows the latter approach, and presents a new method to the automated generation of an initialization sequence for synchronous sequential circuits. We propose a Genetic Algorithm providing a sequence that aims at initializing the highest number of flip flops with the lowest number of vectors. The experimental results show that the approach is feasible to be applied even to the largest benchmark circuits and that it compares well to other known approaches in terms of initialized flip flops and sequence length. Finally, this paper shows how the initialization sequences can be fruitfully exploited by simplifying the ATPG process.

Exploiting logic simulation to improve simulation-based sequential ATPG

Abstract: The constantly increasing circuit size makes the sequential ATPG problem a challenging area even when simulation-based algorithms are exploited. Several techniques have been proposed which mainly resort to logic simulation, reverting to fault simulation only when strictly required. In this paper we present a new Genetic Algorithm-based test generation method which exploits information coming from a logic simulator (e.g., the circuit activity and the reached states) to guide the search process, in particular in the fault excitation phase. Experimental results show the effectiveness of the proposed method when compared with other Genetic Algorithm-based test generators.

SAARA: a simulated annealing algorithm for test pattern generation for digital circuits

Abstract: This paper deals with Automated Test Pattern Generation (ATPG) for large synchronous sequential circuits and describes a new approach based on Simulated Annea ling. Simulation-based ATPG tools have several advantages with respect to deterministic and symbolic ones, especially because they can deal with large circuits. A prototypical system named SAARA is used to assess the effectiveness of the Simulated Annealing approach in terms of test quality and CPU time requirements. Results are reported, showing that SAARA is able to deal with large sequential circuits. A comparison with a state-of-the-art ATPG tool based on a Genetic Algorithm shows that SAARA generally improves the attained results in terms of fault co verage.

Exploiting symbolic techniques within genetic algorithms for power optimization

Abstract: Proposes an optimization algorithm for reducing the power dissipation in a sequential circuit. The encoding of the different states in a finite-state machine is modified to obtain a functionally equivalent circuit that exhibits a reduced power dissipation. The algorithm is based on a newly-proposed power estimation function that is able to quickly give an accurate estimate of the dissipated power without actually synthesizing the circuit. Given this estimate, a genetic algorithm provides a state re-encoding for the circuit. The estimation function is computed in a very efficient way by exploiting some symbolic computations with binary decision diagrams. The algorithm is experimentally shown to provide good results from the power optimization point of view, at a limited cost in terms of area increase, when compared with similar approaches.

Simulation-based verification of network protocols performance

Abstract: Formal verification techniques need to deal with the complexity of the systems being verified. Most often, this problem is solved by taking an abstract model of the system and aiming at a complete verification of an approximation of the system. This paper proposes a complementary verification approach, in which the approximation is introduced into the verification algorithm, instead of the system model: we achieve an approximate verification of a fairly complete and detailed system model. The proposed technique relies on coupling a Genetic Algorithm with a simulator of the system under verification, and is especially suited for verifying performance-related aspects. To prove the effectiveness of our approach, we applied it to the quantitative verification of a network protocol: the TCP protocol operating on a given network. A Genetic Algorithm is able to find a configuration of the traffic over the network that sensitizes a critical problem in the TCP protocol that would be difficult to find both with exact techniques and stochastic ones.

Exploiting high-level descriptions for circuits fault tolerance assessments

Abstract: The paper proposes a new approach to estimate early the fault detection capability of a safety-critical computer-based system from its high-level description. This paper first aims at verifying the correspondence between dependability measures obtained through simulation-based fault injection experiments at different levels of abstraction. Then, we propose Alternative Graphs (AGs) to create lists of malicious faults without expanding the full data flow, whose size can often explode. Fault trees are exploited to improve the results of the high-level fault analysis. To evaluate the effectiveness of the approach, simulation-based fault injection experiments have been done on some benchmark systems described in VHDL language. The approach demonstrates that fault detection analysis performed at a high-level is less CPU time demanding but approximates well the fault detection measures achievable on a low-level system description.