Showing papers by "Matteo Sonza Reorda published in 1998"

A test pattern generation methodology for low power consumption

Abstract: This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the test pattern generation phase and selects a subset of sequences able to reduce the consumed power without reducing the fault coverage. The method is composed of three independent steps: redundant test pattern generation, power consumption measurement, optimal test sequence selection. The experimental results gathered on the ISCAS benchmark circuits show that our approach decreases the power consumption by 70% on average with respect to the original test pattern, generated ignoring the heat dissipation problem.

The selfish gene algorithm: a new evolutionary optimization strategy

Abstract: This paper proposes a new general approach for optimization algorithms in the Evolutionary Computation field. The approach is inspired by the Selfish Gene theory, an interpretation of the Darwinian theory given by the biologist Richard Dawkins, in which the basic element of evolution is the gene, rather than the individual. The paper defines the Selfish Gene Algorithm, which implements such a view of the evolution mechanism. We tested the approach by implementing a Selfish Gene Algorithm on a case study, and we found better results than those provided by a Genetic Algorithm on the same problem and with the same fitness function.

A New Evolutionary Algorithm Inspired by the Selfish Gene Theory

Abstract: This paper proposes a new evolutionary algorithm inspired by the selfish gene theory, an interpretation of the Darwinian natural selection theory given by the biologist Richard Dawkins. In his theory the basic element of evolution is the gene, rather than the individual. The paper defines the selfish gene algorithm, which implements such a view of the evolution mechanism. The strongest and seemingly counter-intuitive assumption of the algorithm is discussed and an experiment that demonstrates its validity is reported. The approach was rested by implementing the selfish gene algorithm on a case study, and it provided better results than those given by a genetic algorithm on the same problem and with the same fitness function.

A new evolutionary algorithm inspired by the selfish gene theory

Abstract: This paper proposes a new evolutionary algorithm inspired by the selfish gene theory, an interpretation of the Darwinian natural selection theory given by the biologist Richard Dawkins. In his theory the basic element of evolution is the gene, rather than the individual. The paper defines the selfish gene algorithm, which implements such a view of the evolution mechanism. The strongest and seemingly counter-intuitive assumption of the algorithm is discussed and an experiment that demonstrates its validity is reported. The approach was rested by implementing the selfish gene algorithm on a case study, and it provided better results than those given by a genetic algorithm on the same problem and with the same fitness function.

An integrated HW and SW fault injection environment for real-time systems

Abstract: This paper describes a system suited to support the Fault Injection process for microprocessor-based embedded systems. The system exploits a low-cost hardware board to monitor the processor status, to activate the fault injection procedure, and to gather information about the fault-free system behavior required to implement a set of fault collapsing rules. The overall environment allows at-speed fault injection experiments with negligible intrusiveness in the target system, and can therefore be used to efficiently evaluate real-time systems dependability.

A fault injection environment for microprocessor-based boards

Abstract: Evaluating the faulty behaviour of low-cost microprocessor-based boards is an increasingly important issue, due to their usage in many safety critical systems To address this issue, the paper describes a software-implemented fault injection system based on the trace exception mode available in most microprocessors The architecture of the complete fault injection environment is proposed, integrating modules for generating a fault list, for performing their injection and for gathering the results, respectively Data gathered from some sample benchmark applications are presented The main advantages of the approach are low cost, good portability, and high efficiency

VEGA: a verification tool based on genetic algorithms

Abstract: While modern state-of-the-art optimization techniques can handle designs with up to hundreds of flip-flops, equivalence verification is still a challenging task in many industrial design flows. This paper presents a new verification methodology that, while sacrificing exactness, is able to handle larger circuits and give designers the opportunity to trade off CPU time with confidence on the result. The proposed methodology is able to fruitfully support an exact verification tool, dramatically increasing the confidence on the validity of an optimization process. A prototypical tool has been developed and preliminary experimental results that support this claim are shown in the paper.

Integrating online and offline testing of a switching memory

Abstract: A circuit used in a telephone switching unit features several test techniques, including BIST, partial scan, and boundary scan. By sharing the same circuitry for both online and offline testing, the design minimizes additional logic while achieving very high fault coverage.

On the identification of optimal cellular automata for built-in self-test of sequential circuits

Abstract: This paper presents a BIST architecture for finite state machines that exploits cellular automata (CA) as pattern generators and signature analyzers. The main advantage of the proposed approach, called C/sup 2/BIST (circular cellular BIST) is that the same CA is used for generation and compaction, thus lowering substantially the area requirements. The configuration of the CA rules is performed through a generic algorithm that is shown to provide good results both in terms of fault coverage and number of reconfigurations. In many cases, no reconfiguration is necessary and the corresponding area occupation is competitive with current BIST approaches.

Experiences in the use of evolutionary techniques for testing digital circuits

Abstract: The generation of test patterns for sequential circuits is one of the most challenging problems arising in the field of Computer-Aided Design for VLSI circuits. In the past decade, Genetic Algorithms have been deeply investigated as a possible approach: several algorithms have been described, and significant improvements have been proposed with respect to their original versions. As a result, GA-based test pattern generators can now effectively compete with other methods, such as topological or symbolic ones. This paper discusses the advantages and disadvantages of GA-based approaches and describes GATTO, a state-of-the-art GA-based test pattern generator. Other algorithms belonging to the same category are outlined as well. The paper puts GATTO and other GA-based tools in perspective, and shows that Evolutionary computation techniques can successfully compete with more traditional approaches, or be integrated with them.© (1998) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

The General Product Machine: a New Model for Symbolic FSM Traversal

Abstract: Proving the equivalence of two Finite State Machines (FSMs) has many applications to synthesis, verification, testing, and diagnosis. Building their product machine is a theoretical framework for equivalence proof. There are some cases where product machine traversal, a necessary and sufficient check, is mandatory. This is much more complex than traversing just one of the component machines. This paper proposes an equivalence-preserving function that transforms the product machine in theGeneral Product Machine (GPM). Using the GPM in symbolic state space traversal reduces the size of the BDDs and makes image computation easier. As a result, GPM traversal is much less expensive than product machine traversal, its cost being close to dealing with a single machine.

A system for evaluating on-line testability at the RT-level

Abstract: This paper presents a system to evaluate the testability of an on-line testable circuit. The system operates at the RT-level, before the logic synthesis step, and allows for an exploration of different testable architectures before committing to the final design. Circuits are modeled as finite state machines, and a set of transformations can be defined inside the system to account for different on-line test strategies. Preliminary experiments show that the information made available by the evaluation system can be used to drive the testable design process towards a better trade-off point.