Showing papers by "Matteo Sonza Reorda published in 2008"

Software-Implemented Hardware Fault Tolerance

Abstract: This book presents the theory behind software-implemented hardware fault tolerance, as well as the practical aspects needed to put it to work on real examples. By evaluating accurately the advantages and disadvantages of the already available approaches, the book provides a guide to developers willing to adopt software-implemented hardware fault tolerance in their applications. Moreover, the book identifies open issues for researchers willing to improve the already available techniques.

Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs

Abstract: Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware hardening is not cost-effective, software implemented hardware fault tolerance (SIHFT) can be a solution to increase SoCs' dependability, but it increases the time for running the hardened application, as well as the memory occupation. In this paper we propose a method that eliminates the memory overhead, by exploiting a new approach to instruction hardening and control flow checking. The proposed method hardens an application online during its execution, without the need for introducing any change in its source code, and is non-intrusive, since it does not require any modification in the main processor's architecture. The method has been tested with two widely used architectures: a microcontroller and a RISC processor, and proven to be suitable for hardening SoCs against transient faults and also for detecting permanent faults.

An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores

Abstract: A large part of microprocessor cores in use today are designed to be cheap and mass produced. The diagnostic process, which is fundamental to improve yield, has to be as cost effective as possible. This paper presents a novel approach to the construction of diagnosis-oriented software-based test sets for microprocessors. The methodology exploits existing manufacturing test sets designed for software-based self-test and improves them by using a new diagnosis-oriented approach. Experimental results are reported in this paper showing the feasibility, robustness, and effectiveness of the approach for diagnosing stuck-at faults on an Intel i8051 processor core.

A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs

Abstract: Software-based self-test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at-speed, low-cost testing, while requiring limited (if any) hardware modifications to the original design However, the method requires effective techniques for generating suitable test programs and for monitoring the results In the case of processor core testing, a particularly complex module to test is the cache controller, due to its limited accessibility and observability In this paper we propose a hybrid methodology that exploits an Infrastructure Intellectual Property (I-IP) to complement an SBST algorithm for testing the data and instruction cache controllers of embedded processors in SoCs In particular, the I-IP may be programmed to monitor the system buses and generate the appropriate feedback about the correct result of the executed programs (in terms of obtained hit or miss operations) The effectiveness of the proposed methodology is evaluated resorting to a sample SoC design

A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions

Abstract: This paper presents an innovative approach for the generation of functional programs to test path- delay faults within microprocessors. The proposed method takes advantage of both the gate- and RT-level description of the processor. The former is used to build binary decision diagrams (BDDs) for deriving fault excitation conditions; the latter is exploited for the automatic generation of test programs able to excite and propagate fault effects, based on an evolutionary algorithm and fast RTL simulation. Experimental results on a simple microcontroller show that the proposed methodology is able to generate suitable test sets in reduced times.

Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs

Abstract: Testing SoC is a challenging task, especially when addressing complex and high- frequency devices. Among the different techniques that can be exploited, software-based selft-test (SBST) emerged as an effective solution, due some advantages it provides (no HW changes, at- speed testing, re-usability); however, the method requires effective techniques for generating suitable test programs. In this paper we face the issue of generating programs to test data caches (in particular their control part): a method is proposed, and some experimental results are provided to assess its effectiveness.

A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores

Abstract: Delay testing is crucial for most microprocessors. Software-based self-test (SBST) methodologies are appealing, but devising effective test programs addressing the true functionally testable paths and assessing their actual coverage are complex tasks. In this paper, we propose a deterministic methodology, based on the analysis of the processor instruction set architecture, for determining rules arbitrating the functional testability of path-delay faults in the data path and control unit of processor cores. Moreover, the performed analysis gives guidelines for generating test programs. A case study on a widely used 8-bit microprocessor is provided.

An novel methodology for reducing SoC test data volume on FPGA-based testers

Abstract: Low-cost test methodologies for systems-on-chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in order to guarantee high test quality, while minimizing application costs. Consequently, low-cost test strategies can be run on testers offering lower performance and/or reduced features with respect to traditional automatic test equipments (ATEs); these equipments are usually referred to as low-cost testers. This paper proposes a methodology for reducing the test data volume for the application of SoC low-cost test procedures. The method exploits a tester architecture organization suitable for SoCs testing, which includes a programmable device: the usage of this configurable block joined to the analysis of test pattern regularities permits minimizing the test data volume, thus improving the tester capabilities. The proposed method relies on test pattern compression at system level and it does not address core level pattern manipulation, as several other previously published works do. Case studies are proposed, which provide data about the application of the proposed methodology to the test of SoCs including self-testable processor and memory cores. IEEE 1149.1 and IEEE 1500 test access mechanisms are considered. The achieved pattern depth reduction ratio is up to about the 64% for the considered case studies.

On the generation of test programs for chip multi-thread computer architectures

Abstract: Within the design arena of modern devices based on cutting-edge processor cores, such as the OpenSPARC T2, the availability of effective verification, validation and test methodologies able to take advantage of high level descriptions of processor cores represents a particular advantage, since they can dramatically reduce the overall time for design and manufacturing, and improve yield and quality. A crucial role is played in this context by methods to generate effective test benches to be used for validation and test (through the software-based self-test, or SBST, paradigm). In this context, we are currently investigating innovative test set generation techniques starting from high level descriptions of processor cores that implement multi-thread architectural paradigms, such as the OpenSPARC T2 core. One of the key points of the T2 processor is the chip multi-threading and multi-core facilities, which have not been extensively considered up to now by traditional SBST strategies. The activity we will report and discuss in the panel focuses in particular on the pick stage existing in the T2 core pipeline. This module is in charge of selecting two threads out of eight for the execution and its correct behavior is essential in order to guarantee both proper functioning and maximum performance. Targeting the thread pick logic is particularly critical, since the test program requires to properly combine the execution of several threads. For example, in this case, it could be essential that every thread reaches a wait state due to all of the different wait conditions, whereas the whole test program limits the overall execution time of the thread.