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Matteo Sonza Reorda

Bio: Matteo Sonza Reorda is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: Fault coverage & Automatic test pattern generation. The author has an hindex of 32, co-authored 295 publications receiving 4525 citations. Previous affiliations of Matteo Sonza Reorda include University of California, Riverside & NXP Semiconductors.


Papers
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Proceedings ArticleDOI
03 Oct 2005
TL;DR: This paper faces the issue of automatically transforming a test set devised for manufacturing test in a testSet suitable for online test, using an Intel 8051 microcontroller.
Abstract: In software-based self-test (SBST), a microprocessor executes a set of test programs devised for detecting the highest possible percentage of faults. The main advantages of this approach are its high defect fault coverage (being performed at-speed) and the reduced cost (since it does not require any change in the processor hardware). SBST can also be used for online test of a microprocessor-based system. However, some additional constraints exist in this case (e.g. in terms of test length and duration, as well as intrusiveness). This paper faces the issue of automatically transforming a test set devised for manufacturing test in a test set suitable for online test. Experimental results are reported on an Intel 8051 microcontroller.

23 citations

Journal ArticleDOI
TL;DR: A functional approach targeting the test of the BPU memory is proposed, which leads to the generation of suitable test programs whose effectiveness is independent of the specific implementation of the TSP, and is validated resorting to an open-source computer architectural simulator.
Abstract: Branch prediction units (BPUs) are highly efficient modules that can significantly decrease the negative impact of branches in pipelined processors. Traditional test solutions, mainly based on Design for Testability techniques, are often inadequate to tackle specific test constraints, such as those found when incoming inspection or online test is considered. Following a functional approach based on running a suitable test program and checking the processor behavior may represent an alternative solution, provided that an effective test algorithm is available for the target unit. In this paper, a functional approach targeting the test of the BPU memory is proposed, which leads to the generation of suitable test programs whose effectiveness is independent of the specific implementation of the BPU. Two very common BPU architectures (branch history table and branch target buffer) are considered. The effectiveness of the approach is validated resorting to an open-source computer architectural simulator. Experimental results show that the proposed method is able to thoroughly test the BPU memory, allowing to transform whichever March algorithm into a corresponding test program; we also provide both theoretical and experimental proofs that the memory and execution time requirements grow linearly with the BPU size.

23 citations

Proceedings ArticleDOI
24 Mar 2014
TL;DR: This work utilizes an ATPG framework for small-delay faults in sequential, non-scan circuits and proposes a method for constraining the input space for generating functional test sequences (i.e., test programs) based on Bounded Model Checking.
Abstract: Functional microprocessor test methods provide several advantages compared to DFT approaches, like reduced chip cost and at-speed execution. However, the automatic generation of functional test patterns is an open issue. In this work we present an approach for the automatic generation of functional microprocessor test sequences for small-delay faults based on Bounded Model Checking. We utilize an ATPG framework for small-delay faults in sequential, non-scan circuits and propose a method for constraining the input space for generating functional test sequences (i.e., test programs). We verify our approach by evaluating the miniMIPS microprocessor. In our experiments we were able to reach over 97 % fault efficiency. To the best of our knowledge, this is the first fully automated approach to functional microprocessor test for small-delay faults.

22 citations

Proceedings ArticleDOI
03 Jan 2001
TL;DR: A distributed bus guardian scheme, where dedicated hardware modules monitor the integrity of the information transmitted over the bus and provide error correction mechanisms is proposed, to enhance the dependability level of the interconnection architecture.
Abstract: This paper presents a methodology for designing system-on-chip interconnection architectures providing a high level of protection from crosstalk and single-event upsets. An event driven simulator enriched with fault injection capabilities is exploited to evaluate the dependability level of the system being designed. The simulation environment supports several bus coding protocols and thus designers can easily evaluate different design alternatives. To enhance the dependability level of the interconnection architecture, we propose a distributed bus guardian scheme, where dedicated hardware modules monitor the integrity of the information transmitted over the bus and provide error correction mechanisms. Preliminary experimental results on a small benchmark system are reported showing the effectiveness of the proposed methodology.

22 citations

01 Jan 1993
TL;DR: A new operator is proposed, whose goal is to include in the genetic mechanism some heuristic knowledge drawn from the already proposed local-optimization techniques, to exploit the benefits of the different operators.
Abstract: A comparative analysis is performed on an experimental basis among four different cross-over operators. In order to exploit the benefits of the different operators, a new one (called Mixed Cross-over) is introduced, trading-off the CPU time requirements and the obtained results. A new operator is then proposed, whose goal is to include in the genetic mechanism some heuristic knowledge drawn from the already proposed local-optimization techniques. The performance of the new operator is discussed.

22 citations


Cited by
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01 Jan 1999
TL;DR: This research organizes, presents, and analyzes contemporary MultiObjective Evolutionary Algorithm research and associated Multiobjective Optimization Problems (MOPs) and uses a consistent MOEA terminology and notation to present a complete, contemporary view of current MOEA "state of the art" and possible future research.
Abstract: : This research organizes, presents, and analyzes contemporary Multiobjective Evolutionary Algorithm (MOEA) research and associated Multiobjective Optimization Problems (MOPs). Using a consistent MOEA terminology and notation, each cited MOEAs' key factors are presented in tabular form for ease of MOEA identification and selection. A detailed quantitative and qualitative MOEA analysis is presented, providing a basis for conclusions about various MOEA-related issues. The traditional notion of building blocks is extended to the MOP domain in an effort to develop more effective and efficient MOEAs. Additionally, the MOEA community's limited test suites contain various functions whose origins and rationale for use are often unknown. Thus, using general test suite guidelines appropriate MOEA test function suites are substantiated and generated. An experimental methodology incorporating a solution database and appropriate metrics is offered as a proposed evaluation framework allowing absolute comparisons of specific MOEA approaches. Taken together, this document's classifications, analyses, and new innovations present a complete, contemporary view of current MOEA "state of the art" and possible future research. Researchers with basic EA knowledge may also use part of it as a largely self-contained introduction to MOEAs.

1,287 citations

Book
31 Jan 1993
TL;DR: This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.
Abstract: From the Publisher: This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

927 citations

Journal ArticleDOI
TL;DR: This paper presents crossover and mutation operators, developed to tackle the Travelling Salesman Problem with Genetic Algorithms with different representations such as: binary representation, path representation, adjacency representation, ordinal representation and matrix representation.
Abstract: This paper is the result of a literature study carried out by the authors. It is a review of the different attempts made to solve the Travelling Salesman Problem with Genetic Algorithms. We present crossover and mutation operators, developed to tackle the Travelling Salesman Problem with Genetic Algorithms with different representations such as: binary representation, path representation, adjacency representation, ordinal representation and matrix representation. Likewise, we show the experimental results obtained with different standard examples using combination of crossover and mutation operators in relation with path representation.

839 citations

Journal ArticleDOI
TL;DR: A taxonomy of hybrid metaheuristics is presented in an attempt to provide a common terminology and classification mechanisms and is also applicable to most types of heuristics and exact optimization algorithms.
Abstract: Hybrid metaheuristics have received considerable interest these recent years in the field of combinatorial optimization. A wide variety of hybrid approaches have been proposed in the literature. In this paper, a taxonomy of hybrid metaheuristics is presented in an attempt to provide a common terminology and classification mechanisms. The taxonomy, while presented in terms of metaheuristics, is also applicable to most types of heuristics and exact optimization algorithms. As an illustration of the usefulness of the taxonomy an annoted bibliography is given which classifies a large number of hybrid approaches according to the taxonomy.

829 citations

Journal Article
TL;DR: In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.
Abstract: We consider a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants. In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.

775 citations