M
Matteo Sonza Reorda
Researcher at Polytechnic University of Turin
Publications - 340
Citations - 5043
Matteo Sonza Reorda is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: Fault coverage & Automatic test pattern generation. The author has an hindex of 32, co-authored 295 publications receiving 4525 citations. Previous affiliations of Matteo Sonza Reorda include University of California, Riverside & NXP Semiconductors.
Papers
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Journal ArticleDOI
Scan-Chain Intra-Cell Aware Testing
A. Touati,Alberto Bosio,Patrick Girard,Arnaud Virazel,Paolo Bernardi,Matteo Sonza Reorda,Etienne Auvray +6 more
TL;DR: This paper demonstrates that by combining test vectors generated by a commercial ATPG to detect stuck-at and delay faults, plus a fragment of extra test patterns generated to specifically target the escaped defects, one can obtain a higher intra-cell defect coverage and a shorter test time than by straightforwardly using an ATPG which directly targets these defects.
Proceedings ArticleDOI
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
TL;DR: A new mechanism for grading functional test program path-delay coverage relying on FPGA-based emulation, based on suitable instrumentation of the circuit structure and exploiting ad hoc modules to minimize the host performance requirements stemming from the experiment management is proposed.
Book ChapterDOI
Advanced technologies for transient faults detection and compensation
TL;DR: In this article, the authors present the origin of transient faults, the propagation mechanism, and the models devised to represent them and discuss the state-of-the-art design techniques that can be used to detect and correct transient faults.
Proceedings ArticleDOI
Challenges of Reliability Assessment and Enhancement in Autonomous Systems
TL;DR: In this paper, the authors make an overview of reliability challenges for intelligence implementation in autonomous systems enabled by HW backbones such as neuromorphic architectures, approximate computing architectures, GPUs, tensor processing units (TPUs) and SoC FPGAs.
Book ChapterDOI
A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits
TL;DR: A new parallel version of an existing GA-based ATPG, which exploits competing sub-populations to overcome these problems and is able to significantly improve the results quality at the expense of increased CPU time requirements.