: This research organizes, presents, and analyzes contemporary Multiobjective Evolutionary Algorithm (MOEA) research and associated Multiobjective Optimization Problems (MOPs). Using a consistent MOEA terminology and notation, each cited MOEAs' key factors are presented in tabular form for ease of MOEA identification and selection. A detailed quantitative and qualitative MOEA analysis is presented, providing a basis for conclusions about various MOEA-related issues. The traditional notion of building blocks is extended to the MOP domain in an effort to develop more effective and efficient MOEAs. Additionally, the MOEA community's limited test suites contain various functions whose origins and rationale for use are often unknown. Thus, using general test suite guidelines appropriate MOEA test function suites are substantiated and generated. An experimental methodology incorporating a solution database and appropriate metrics is offered as a proposed evaluation framework allowing absolute comparisons of specific MOEA approaches. Taken together, this document's classifications, analyses, and new innovations present a complete, contemporary view of current MOEA "state of the art" and possible future research. Researchers with basic EA knowledge may also use part of it as a largely self-contained introduction to MOEAs.

Multiobjective evolutionary algorithms: classifications, analyses, and new innovations

From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

Algorithms for VLSI Physical Design Automation

This paper is the result of a literature study carried out by the authors. It is a review of the different attempts made to solve the Travelling Salesman Problem with Genetic Algorithms. We present crossover and mutation operators, developed to tackle the Travelling Salesman Problem with Genetic Algorithms with different representations such as: binary representation, path representation, adjacency representation, ordinal representation and matrix representation. Likewise, we show the experimental results obtained with different standard examples using combination of crossover and mutation operators in relation with path representation.

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Genetic Algorithms for the Travelling Salesman Problem: A Review of Representations and Operators

Hybrid metaheuristics have received considerable interest these recent years in the field of combinatorial optimization. A wide variety of hybrid approaches have been proposed in the literature. In this paper, a taxonomy of hybrid metaheuristics is presented in an attempt to provide a common terminology and classification mechanisms. The taxonomy, while presented in terms of metaheuristics, is also applicable to most types of heuristics and exact optimization algorithms.

As an illustration of the usefulness of the taxonomy an annoted bibliography is given which classifies a large number of hybrid approaches according to the taxonomy.

A Taxonomy of Hybrid Metaheuristics

We consider a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants. In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.

Interpolation and SAT-based model checking

Control flow checking through embedded debug interface

This paper presents a BIST architecture for finite state machines that exploits cellular automata (CA) as pattern generators and signature analyzers. The main advantage of the proposed approach, called C/sup 2/BIST (circular cellular BIST) is that the same CA is used for generation and compaction, thus lowering substantially the area requirements. The configuration of the CA rules is performed through a generic algorithm that is shown to provide good results both in terms of fault coverage and number of reconfigurations. In many cases, no reconfiguration is necessary and the corresponding area occupation is competitive with current BIST approaches.

On the identification of optimal cellular automata for built-in self-test of sequential circuits

Previous studies have suggested that many multiple stuck-at faults are detected by the test patterns generated to detect single stuck-at faults, but a fault simulation is often impossible, as their number grows and becomes enormous as real-sized circuits are considered. Thus, rules are needed to decrease their number by neglecting those that are surely detected by the patterns generated for single stuck-ats. A procedure is first given for establishing whether a multiple stuck-at fault is detected by a pattern. Then this procedure is used to prove a set of rules that allows the size of the fault list to be decreased significantly. Experimental results on the standard set of combinational benchmark circuits are provided, showing the effectiveness of the approach. >

Improved techniques for multiple stuck-at fault analysis using single stuck-at fault test sets

GPGPUs have been increasingly successful in the past years in many application domains, due to their high parallel processing capabilities and energy performance. More recently, they started to be used in areas (such as automotive) where safety is also an important parameter. However, their architectural complexity and advanced technology level create challenges when matching the required reliability targets. This requires devising solutions to perform in-field test, thus allowing the systematic detection of possible permanent faults. These faults are caused by aging or external factors that affect the application execution and potentially generate critical misbehaviors. Moreover, effective in-field test techniques oriented to verify the integrity of GPGPU modules during in-field operation are still missed. In this work, we propose a method to generate self-test procedures able to detect all static faults affecting the scheduler memory existing in each streaming multiprocessor (SM) of a GPGPU. NVIDIA CUDA-C is selected as high-level programing language. The experimental results are obtained employing the NVIDIA Nsight Debugger on a NVIDIA-GEFORCE GTX GPU and a memory fault simulator.

On the in-field test of the GPGPU scheduler memory

This article deals with the generation of exact diagnostic trees for real-size synchronous sequential circuits. Starting from existing detection-oriented test patterns, a modified fault simulator is used for assessing their diagnostic power, which, in general, is not satisfactory. A diagnostic procedure for improving it is described that successfully exploits symbolic FSM equivalence proof algorithms. In order to resort to costly techniques, such as product machine traversal, only when really needed, special checks are performed to verify combinational identity and identity on reachable states. As all faults are attributed to theirequivalence class, a complete and exact diagnostic tree can be built. Experimental results on ISCAS'89 circuits show the feasibility of the approach and support the claim that, for the first time, diagnosing real-world synchronous sequential circuits has become feasible.

Matteo Sonza Reorda

Papers

Control flow checking through embedded debug interface

On the identification of optimal cellular automata for built-in self-test of sequential circuits

Improved techniques for multiple stuck-at fault analysis using single stuck-at fault test sets

On the in-field test of the GPGPU scheduler memory

An Approach to Sequential Circuit Diagnosis Based on Formal Verification Techniques