Matteo Sonza Reorda

Bio: Matteo Sonza Reorda is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: Fault coverage & Automatic test pattern generation. The author has an hindex of 32, co-authored 295 publications receiving 4525 citations. Previous affiliations of Matteo Sonza Reorda include University of California, Riverside & NXP Semiconductors.

Experiences in the use of evolutionary techniques for testing digital circuits

Abstract: The generation of test patterns for sequential circuits is one of the most challenging problems arising in the field of Computer-Aided Design for VLSI circuits. In the past decade, Genetic Algorithms have been deeply investigated as a possible approach: several algorithms have been described, and significant improvements have been proposed with respect to their original versions. As a result, GA-based test pattern generators can now effectively compete with other methods, such as topological or symbolic ones. This paper discusses the advantages and disadvantages of GA-based approaches and describes GATTO, a state-of-the-art GA-based test pattern generator. Other algorithms belonging to the same category are outlined as well. The paper puts GATTO and other GA-based tools in perspective, and shows that Evolutionary computation techniques can successfully compete with more traditional approaches, or be integrated with them.© (1998) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

SW-based transparent in-field memory testing

Abstract: With continuous technology scaling, both quality and reliability are becoming major concerns for ICs due to extreme variations, non-ideal voltage scaling, etc. (not to mention the business pressure leading to shorter-time to market). One-time-factory manufacturing test is not sufficient anymore, and in-field testing (e.g., periodically, at power-on, during idle times) is becoming mandatory. Due to the strict constraints of in-field test, transparent BIST is extremely attractive, since it allows to minimize test invasiveness. This paper presents a cheap, high quality and practical SW-based transparent in-field test approach for memories within a system. Instead of using hardware BIST, the proposed scheme re-uses the CPU to perform infield testing for all memories within the system. All quality metrics of the proposed solution (such as defect coverage, test time and code size) are analyzed. Case studies using the ARM instruction set architecture are provided to demonstrate the applicability of the solution. With the proposed approach no hardware BIST is necessary and speed-related faults are tackled, whereas results show the test time complexity of the SW-based transparent tests is the same as the one of the standard hardware BIST test. Moreover, data previously present in the memory is not corrupted with, in average, only a 30% increase in test program size with respect to non-transparent SW-based test.

Evaluating the Impact of DfM Library Optimizations on Alpha-induced SEU Sensitivity in a Microprocessor Core

Abstract: This paper presents and discusses the results of Alpha Single Event Upset (SEU) tests on an embedded 8051 microprocessor core implemented using three different standard cell libraries. Each library is based on a different Design for Manufacturability (DfM) optimization strategy; our goal is to understand how these strategies may affect the device sensitivity to alpha-induced Soft Errors. The three implementations are tested resorting to advanced Design for Testability (DfT) methodologies and radiation experiments results are compared. Electrical simulations of flip-flops are finally performed to propose physical motivations to the observed phenomena.

Speeding-Up Fault Injection Campaigns in VHDL Models

Abstract: Simulation-based Fault Injection in VHDL descriptions is increasingly common due to the popularity of top-down design flows exploiting this language. This paper presents some techniques for reducing the time to perform the required simulation experiments. Static and dynamic methods are proposed to analyze the list of faults to be injected, removing faults as soon as their behavior is known. Common features available in most VHDL simulation environments are also exploited. Experimental results show that the proposed techniques are able to reduce the time required by a typical Fault Injection campaign by a factor ranging from 43.9% to 96.6%.

Multiobjective evolutionary algorithms: classifications, analyses, and new innovations

Abstract: : This research organizes, presents, and analyzes contemporary Multiobjective Evolutionary Algorithm (MOEA) research and associated Multiobjective Optimization Problems (MOPs). Using a consistent MOEA terminology and notation, each cited MOEAs' key factors are presented in tabular form for ease of MOEA identification and selection. A detailed quantitative and qualitative MOEA analysis is presented, providing a basis for conclusions about various MOEA-related issues. The traditional notion of building blocks is extended to the MOP domain in an effort to develop more effective and efficient MOEAs. Additionally, the MOEA community's limited test suites contain various functions whose origins and rationale for use are often unknown. Thus, using general test suite guidelines appropriate MOEA test function suites are substantiated and generated. An experimental methodology incorporating a solution database and appropriate metrics is offered as a proposed evaluation framework allowing absolute comparisons of specific MOEA approaches. Taken together, this document's classifications, analyses, and new innovations present a complete, contemporary view of current MOEA "state of the art" and possible future research. Researchers with basic EA knowledge may also use part of it as a largely self-contained introduction to MOEAs.

Algorithms for VLSI Physical Design Automation

Abstract: From the Publisher: This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

Genetic Algorithms for the Travelling Salesman Problem: A Review of Representations and Operators

Abstract: This paper is the result of a literature study carried out by the authors. It is a review of the different attempts made to solve the Travelling Salesman Problem with Genetic Algorithms. We present crossover and mutation operators, developed to tackle the Travelling Salesman Problem with Genetic Algorithms with different representations such as: binary representation, path representation, adjacency representation, ordinal representation and matrix representation. Likewise, we show the experimental results obtained with different standard examples using combination of crossover and mutation operators in relation with path representation.

A Taxonomy of Hybrid Metaheuristics

Abstract: Hybrid metaheuristics have received considerable interest these recent years in the field of combinatorial optimization. A wide variety of hybrid approaches have been proposed in the literature. In this paper, a taxonomy of hybrid metaheuristics is presented in an attempt to provide a common terminology and classification mechanisms. The taxonomy, while presented in terms of metaheuristics, is also applicable to most types of heuristics and exact optimization algorithms. As an illustration of the usefulness of the taxonomy an annoted bibliography is given which classifies a large number of hybrid approaches according to the taxonomy.

Interpolation and SAT-based model checking

Abstract: We consider a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants. In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.