: This research organizes, presents, and analyzes contemporary Multiobjective Evolutionary Algorithm (MOEA) research and associated Multiobjective Optimization Problems (MOPs). Using a consistent MOEA terminology and notation, each cited MOEAs' key factors are presented in tabular form for ease of MOEA identification and selection. A detailed quantitative and qualitative MOEA analysis is presented, providing a basis for conclusions about various MOEA-related issues. The traditional notion of building blocks is extended to the MOP domain in an effort to develop more effective and efficient MOEAs. Additionally, the MOEA community's limited test suites contain various functions whose origins and rationale for use are often unknown. Thus, using general test suite guidelines appropriate MOEA test function suites are substantiated and generated. An experimental methodology incorporating a solution database and appropriate metrics is offered as a proposed evaluation framework allowing absolute comparisons of specific MOEA approaches. Taken together, this document's classifications, analyses, and new innovations present a complete, contemporary view of current MOEA "state of the art" and possible future research. Researchers with basic EA knowledge may also use part of it as a largely self-contained introduction to MOEAs.

Multiobjective evolutionary algorithms: classifications, analyses, and new innovations

From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

Algorithms for VLSI Physical Design Automation

This paper is the result of a literature study carried out by the authors. It is a review of the different attempts made to solve the Travelling Salesman Problem with Genetic Algorithms. We present crossover and mutation operators, developed to tackle the Travelling Salesman Problem with Genetic Algorithms with different representations such as: binary representation, path representation, adjacency representation, ordinal representation and matrix representation. Likewise, we show the experimental results obtained with different standard examples using combination of crossover and mutation operators in relation with path representation.

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Genetic Algorithms for the Travelling Salesman Problem: A Review of Representations and Operators

Hybrid metaheuristics have received considerable interest these recent years in the field of combinatorial optimization. A wide variety of hybrid approaches have been proposed in the literature. In this paper, a taxonomy of hybrid metaheuristics is presented in an attempt to provide a common terminology and classification mechanisms. The taxonomy, while presented in terms of metaheuristics, is also applicable to most types of heuristics and exact optimization algorithms.

As an illustration of the usefulness of the taxonomy an annoted bibliography is given which classifies a large number of hybrid approaches according to the taxonomy.

A Taxonomy of Hybrid Metaheuristics

We consider a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants. In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.

Interpolation and SAT-based model checking

The growing adoption of SRAM-based field programmable gate arrays (FPGAs) in safety-critical applications demands for efficient methodologies for evaluating their reliability. Single event upsets (SEUs) affecting the configuration memory of SRAM-based FPGAs are a major concern, since they can permanently affect the function implemented by the device. We exploited a fault-injection environment developed at our institution to analyze the impact of such faults on SRAM-based FPGAs when fault tolerant design techniques are adopted. The experimental results allow quantitative evaluations of the effects of these faults, and show that the sensitivity of the TMR design technique mainly depends on the characteristics of the adopted TMR architecture in terms of placing and routing.

On the evaluation of SEU sensitiveness in SRAM-based FPGAs

This paper proposes a new general approach for optimization algorithms in the Evolutionary Computation field. The approach is inspired by the Selfish Gene theory, an interpretation of the Darwinian theory given by the biologist Richard Dawkins, in which the basic element of evolution is the gene, rather than the individual. The paper defines the Selfish Gene Algorithm, which implements such a view of the evolution mechanism. We tested the approach by implementing a Selfish Gene Algorithm on a case study, and we found better results than those provided by a Genetic Algorithm on the same problem and with the same fitness function.

The selfish gene algorithm: a new evolutionary optimization strategy

Simulation-based fault injection in VHDL descriptions is increasingly common due to the popularity of top-down design flows exploiting this language. However, the large CPU time required to perform VHDL simulations often represents a major drawback stemming from the adoption of this method. This paper presents some techniques for reducing the time to perform the fault injection experiments. Static and dynamic methods are proposed to analyze the list of faults to be injected, and for removing faults as soon as their behaviour is known. Common features available in most VHDL simulation environments are also exploited. Experimental results show that the proposed techniques are able to reduce the time required by a typical fault injection campaign by a factor ranging from 51% to 96%.

New techniques for accelerating fault injection in VHDL descriptions

High-quality memory testing is increasingly important, especially when RAMs and ROMs are deeply embedded in bigger systems, as the techniques based on control and observation points fail. Adopting a built-in self-test scheme for deeply embedded memories seems advantageous and industrial experience at Italtel, a telecom company, confirms it. The scheme implements in hardware the test pattern generation algorithm proposed by R. Nair, S.M. Thatte, and J.A. Abraham \cite{NTAb78}, extending it to word-based memories. Area overhead, performance degradation, additional pins, and test time are minimal, whereas we guarantee high fault coverage for the significant failure modes and full testability of the BIST hardware, as the experimental results confirm.

Industrial BIST of embedded RAMs

The widespread adoption of VLSI devices for safety-critical applications asks for effective tools for the evaluation and validation of their reliability. Fault injection is commonly adopted for this task, and the effectiveness of the adopted techniques is therefore a key factor for the reliability of the final products. In this paper we present new techniques for exploiting FPGAs to speed-up fault injection in VLSI circuits. Thanks to the suitable circuitry added to the original circuit, transient faults affecting memory elements in the circuit can be considered. The proposed approach allows performing fault injection campaigns that are comparable to those performed with hardware-based techniques in terms of speed, but shows a much higher flexibility in terms of supported fault models.

Matteo Sonza Reorda

Papers

On the evaluation of SEU sensitiveness in SRAM-based FPGAs

The selfish gene algorithm: a new evolutionary optimization strategy

New techniques for accelerating fault injection in VHDL descriptions

Industrial BIST of embedded RAMs

Exploiting FPGA for accelerating fault injection experiments