Matteo Sonza Reorda

Bio: Matteo Sonza Reorda is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: Fault coverage & Automatic test pattern generation. The author has an hindex of 32, co-authored 295 publications receiving 4525 citations. Previous affiliations of Matteo Sonza Reorda include University of California, Riverside & NXP Semiconductors.

Microarchitectural Reliability Evaluation of a Block Scheduling Controller in GPUs

Abstract: Graphic Processing Units (GPUs) are currently adopted in several domains with substantial reliability requirements, such as in automotive and robotics. Thus, evaluating the impact of possible faults affecting the internal components of a device is a crucial step towards developing certified products according to industrial standards (i.e., ISO26262). The block scheduling controllers play an important role in resource management and task operation in GPUs. However, understanding the sensitivity to faults of such modules is crucial in the development of mitigation mechanisms and effective countermeasures. This work evaluates the impact of transient faults on the block controller in a GPU. For this purpose, we extended a low-level micro-architecture GPU model (FlexGripPlus) to support the management of the different execution cores (i.e., the Streaming Multiprocessors or SIMD Engines) and allow the analysis of fault effects. A set of typical workloads were employed in the reliability evaluation. The experimental results show that the most critical stages for faults in the scheduler are those arising during the device's configuration and the exchange of tasks from an application. Moreover, when considering faults in the controller, multi-core GPUs appear to be less sensitive to faults than single-core GPUs. Finally, the parallel distribution of tasks (in blocks) also plays a significant role in the vulnerability to faults of the scheduler.

Simulation-based verification of network protocols performance

Abstract: Formal verification techniques need to deal with the complexity of the systems being verified. Most often, this problem is solved by taking an abstract model of the system and aiming at a complete verification of an approximation of the system. This paper proposes a complementary verification approach, in which the approximation is introduced into the verification algorithm, instead of the system model: we achieve an approximate verification of a fairly complete and detailed system model. The proposed technique relies on coupling a Genetic Algorithm with a simulator of the system under verification, and is especially suited for verifying performance-related aspects. To prove the effectiveness of our approach, we applied it to the quantitative verification of a network protocol: the TCP protocol operating on a given network. A Genetic Algorithm is able to find a configuration of the traffic over the network that sensitizes a critical problem in the TCP protocol that would be difficult to find both with exact techniques and stochastic ones.

Maximizing the Switching Activity of Different Modules Within a Processor Core via Evolutionary Techniques

Abstract: One key aspect to be considered during device testing is the minimization of the switching activity of the circuit under test (CUT), thus avoiding possible problems stemming from overheating it. But there are also scenarios, where the maximization of certain circuits' modules switching activity could be proven useful (e.g., during Burn-In) in order to exercise the circuit under extreme operating conditions in terms of temperature (and temperature gradients). Resorting to a functional approach based on Software-based Self-test guarantees that the high induced activity cannot damage the CUT nor produce any yield loss. However, the generation of effective suitable test programs remains a challenging task. In this paper, we consider a scenario where the modules to be stressed are sub-modules of a fully pipelined processor. We present a technique, based on an evolutionary approach, able to automatically generate stress test programs, i.e., sequences of instructions achieving a high toggling activity in the target module. With respect to previous approaches, the generated sequences are short and repeatable, thus guaranteeing their easy usability to stress a module (and increase its temperature). The processor we used for our experiments is the Open RISC 1200. Results demonstrate that the proposed method is effective in achieving a high value of sustained toggling activity with short (3 instructions) and repeatable sequences.

Exploiting high-level descriptions for circuits fault tolerance assessments

Abstract: The paper proposes a new approach to estimate early the fault detection capability of a safety-critical computer-based system from its high-level description. This paper first aims at verifying the correspondence between dependability measures obtained through simulation-based fault injection experiments at different levels of abstraction. Then, we propose Alternative Graphs (AGs) to create lists of malicious faults without expanding the full data flow, whose size can often explode. Fault trees are exploited to improve the results of the high-level fault analysis. To evaluate the effectiveness of the approach, simulation-based fault injection experiments have been done on some benchmark systems described in VHDL language. The approach demonstrates that fault detection analysis performed at a high-level is less CPU time demanding but approximates well the fault detection measures achievable on a low-level system description.

Multiobjective evolutionary algorithms: classifications, analyses, and new innovations

Abstract: : This research organizes, presents, and analyzes contemporary Multiobjective Evolutionary Algorithm (MOEA) research and associated Multiobjective Optimization Problems (MOPs). Using a consistent MOEA terminology and notation, each cited MOEAs' key factors are presented in tabular form for ease of MOEA identification and selection. A detailed quantitative and qualitative MOEA analysis is presented, providing a basis for conclusions about various MOEA-related issues. The traditional notion of building blocks is extended to the MOP domain in an effort to develop more effective and efficient MOEAs. Additionally, the MOEA community's limited test suites contain various functions whose origins and rationale for use are often unknown. Thus, using general test suite guidelines appropriate MOEA test function suites are substantiated and generated. An experimental methodology incorporating a solution database and appropriate metrics is offered as a proposed evaluation framework allowing absolute comparisons of specific MOEA approaches. Taken together, this document's classifications, analyses, and new innovations present a complete, contemporary view of current MOEA "state of the art" and possible future research. Researchers with basic EA knowledge may also use part of it as a largely self-contained introduction to MOEAs.

Algorithms for VLSI Physical Design Automation

Abstract: From the Publisher: This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

Genetic Algorithms for the Travelling Salesman Problem: A Review of Representations and Operators

Abstract: This paper is the result of a literature study carried out by the authors. It is a review of the different attempts made to solve the Travelling Salesman Problem with Genetic Algorithms. We present crossover and mutation operators, developed to tackle the Travelling Salesman Problem with Genetic Algorithms with different representations such as: binary representation, path representation, adjacency representation, ordinal representation and matrix representation. Likewise, we show the experimental results obtained with different standard examples using combination of crossover and mutation operators in relation with path representation.

A Taxonomy of Hybrid Metaheuristics

Abstract: Hybrid metaheuristics have received considerable interest these recent years in the field of combinatorial optimization. A wide variety of hybrid approaches have been proposed in the literature. In this paper, a taxonomy of hybrid metaheuristics is presented in an attempt to provide a common terminology and classification mechanisms. The taxonomy, while presented in terms of metaheuristics, is also applicable to most types of heuristics and exact optimization algorithms. As an illustration of the usefulness of the taxonomy an annoted bibliography is given which classifies a large number of hybrid approaches according to the taxonomy.

Interpolation and SAT-based model checking

Abstract: We consider a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants. In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.