Matteo Sonza Reorda

Bio: Matteo Sonza Reorda is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: Fault coverage & Automatic test pattern generation. The author has an hindex of 32, co-authored 295 publications receiving 4525 citations. Previous affiliations of Matteo Sonza Reorda include University of California, Riverside & NXP Semiconductors.

Evaluating the impact of Permanent Faults in a GPU running a Deep Neural Network

Abstract: Currently, Deep Neural Networks (DNNs) are fun-damental computational structures deployed in a wide range of modern application domains (e.g., data analysis, healthcare, automotive, robotics). The computational complexity is inherent in these cognitive models, which demand high-performance devices like Graphics Processing Units (GPUs). Therefore, the implementation of DNNs on GPU devices is becoming increasingly frequent, even for cutting-edge safety-critical applications (e.g., autonomous and semi-autonomous cars). Thus, the reliability evaluation of these applications is mandatory because several phenomena (including aging) may produce permanent defects in the GPU, thus inducing the DNN to produce wrong results. Until now, the effects of permanent faults on DNNs have been mainly investigated at the application level, only, e.g., acting on the parameters of the network. This paper presents an environment allowing for the first time a more detailed experimental evaluation of the impact of permanent faults in a GPU on the reliability of a DNN running on it, based on considering faults at the architectural level. The results of the fault injection campaigns we performed on the GPU register files are compared with those at the application level, proving that the latter ones are generally optimistic.

Exact probabilistic testability measures for multi-output circuits

Abstract: The computation of probabilistic testability measures has become increasingly important and some methods have been proposed, although the exact solution of the problem is NP-hard. An exact analytical method for singleoutput combinational circuits is extended to deal with multi-output circuits. Such circuits are reduced to singleoutput ones by introducing a dummy gate, the “X-gate,” and applying to the resulting graph the analysis based on supergates.

On the generation of test programs for chip multi-thread computer architectures

Abstract: Within the design arena of modern devices based on cutting-edge processor cores, such as the OpenSPARC T2, the availability of effective verification, validation and test methodologies able to take advantage of high level descriptions of processor cores represents a particular advantage, since they can dramatically reduce the overall time for design and manufacturing, and improve yield and quality. A crucial role is played in this context by methods to generate effective test benches to be used for validation and test (through the software-based self-test, or SBST, paradigm). In this context, we are currently investigating innovative test set generation techniques starting from high level descriptions of processor cores that implement multi-thread architectural paradigms, such as the OpenSPARC T2 core. One of the key points of the T2 processor is the chip multi-threading and multi-core facilities, which have not been extensively considered up to now by traditional SBST strategies. The activity we will report and discuss in the panel focuses in particular on the pick stage existing in the T2 core pipeline. This module is in charge of selecting two threads out of eight for the execution and its correct behavior is essential in order to guarantee both proper functioning and maximum performance. Targeting the thread pick logic is particularly critical, since the test program requires to properly combine the execution of several threads. For example, in this case, it could be essential that every thread reaches a wait state due to all of the different wait conditions, whereas the whole test program limits the overall execution time of the thread.

In-field Data Collection System through Logic BIST for large Automotive Systems-on-Chip

Abstract: Embedded nano-electronic systems are becoming more prevalent in people's daily lives. As a result, chip and embedded system manufacturing has become increasingly complicated and huge in recent years. Considering safety-critical sectors, such as automotive, it is evident how managing system anomalies and defects becomes vital. Thus, it is necessary to develop and investigate innovative methodologies that can guarantee high reliability despite modern Systems-on-Chip's complexity in critical safety fields. Significant attempts were made to market incredibly reliable microelectronic components. In order to ensure the reliability of the devices, the Automotive field has also started focusing on collecting large amounts of data from car fleets. The data are collected in-field during the life cycle of the devices and create effective feedback for designers and manufacturers. This paper proposes a methodology to store and collect data from key-on and key-off tests performed by Logic BIST for an industrial case study produced by STMicroelectronics.

Multiobjective evolutionary algorithms: classifications, analyses, and new innovations

Abstract: : This research organizes, presents, and analyzes contemporary Multiobjective Evolutionary Algorithm (MOEA) research and associated Multiobjective Optimization Problems (MOPs). Using a consistent MOEA terminology and notation, each cited MOEAs' key factors are presented in tabular form for ease of MOEA identification and selection. A detailed quantitative and qualitative MOEA analysis is presented, providing a basis for conclusions about various MOEA-related issues. The traditional notion of building blocks is extended to the MOP domain in an effort to develop more effective and efficient MOEAs. Additionally, the MOEA community's limited test suites contain various functions whose origins and rationale for use are often unknown. Thus, using general test suite guidelines appropriate MOEA test function suites are substantiated and generated. An experimental methodology incorporating a solution database and appropriate metrics is offered as a proposed evaluation framework allowing absolute comparisons of specific MOEA approaches. Taken together, this document's classifications, analyses, and new innovations present a complete, contemporary view of current MOEA "state of the art" and possible future research. Researchers with basic EA knowledge may also use part of it as a largely self-contained introduction to MOEAs.

Algorithms for VLSI Physical Design Automation

Abstract: From the Publisher: This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

Genetic Algorithms for the Travelling Salesman Problem: A Review of Representations and Operators

Abstract: This paper is the result of a literature study carried out by the authors. It is a review of the different attempts made to solve the Travelling Salesman Problem with Genetic Algorithms. We present crossover and mutation operators, developed to tackle the Travelling Salesman Problem with Genetic Algorithms with different representations such as: binary representation, path representation, adjacency representation, ordinal representation and matrix representation. Likewise, we show the experimental results obtained with different standard examples using combination of crossover and mutation operators in relation with path representation.

A Taxonomy of Hybrid Metaheuristics

Abstract: Hybrid metaheuristics have received considerable interest these recent years in the field of combinatorial optimization. A wide variety of hybrid approaches have been proposed in the literature. In this paper, a taxonomy of hybrid metaheuristics is presented in an attempt to provide a common terminology and classification mechanisms. The taxonomy, while presented in terms of metaheuristics, is also applicable to most types of heuristics and exact optimization algorithms. As an illustration of the usefulness of the taxonomy an annoted bibliography is given which classifies a large number of hybrid approaches according to the taxonomy.

Interpolation and SAT-based model checking

Abstract: We consider a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants. In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.