Matteo Sonza Reorda

Bio: Matteo Sonza Reorda is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: Fault coverage & Automatic test pattern generation. The author has an hindex of 32, co-authored 295 publications receiving 4525 citations. Previous affiliations of Matteo Sonza Reorda include University of California, Riverside & NXP Semiconductors.

Test Solution for Heatsinks in Power Electronics Applications

Abstract: Power electronics technology is widely used in several areas, such as in the railways, automotive, electric vehicles, and renewable energy sectors Some of these applications are safety critical, eg, in the automotive domain The heat produced by power devices must be efficiently dissipated to allow them to work within their operational thermal limits Moreover, numerous ageing effects are due to thermal stress, which causes mechanical issues Therefore, the reliability of a circuit depends on its dissipation system, even if it consists of a simple passive heatsink mounted on the power device During the Printed Circuit Board (PCB) production, an incorrect assembly of the heatsink can cause a worse heat dissipation with a significant increase of the junction temperatures (Tj) In this paper, three possible test strategies are compared for testing the correct assembling of heatsinks The considered strategies are used at the PCB end-manufacturing The effectiveness of the different test methods considered is assessed on a case study corresponding to a Power Supply Unit (PSU)

A New Method to Generate Software Test Libraries for In-Field GPU Testing Resorting to High-Level Languages

Abstract: Self-Test Libraries (STLs) are widely used by companies for in-field fault detection in CPU devices. Their usage is now extending to GPUs, due to their increasing adoption in safety-critical applications. Using STLs provided by GPU manufacturers, system companies can effectively test these devices during their operative life, as required by functional safety standards. In the automotive domain, GPUs are often used to process a high amount of sensitive information in real-time (e.g., object recognition and path tracking). Thus, GPU devices in this field must guarantee functional safety features (e.g., ISO26262) by using one or more functional safety mechanisms. This paper presents a methodology to develop STLs resorting to High-Level Languages (HLLs) (e.g., CUDA), reducing the complexity of encoding at the assembly level. Moreover, we describe the main advantages and discuss the challenges and constraints when developing STLs with HLLs for GPUs. In particular, we describe those cases that demand the usage of a Low-Level Language (LLL). Additionally, we highlight a method to develop STLs resorting to HLLs, at least for some modules. The FlexGripPlus GPU model was employed to evaluate and validate the proposed strategies experimentally. The results show that STLs based on HLLs can be effectively developed for regular modules in the GPU.

Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries

Abstract: In-field test of integrated circuits using Self-Test Libraries (STLs) is a widely used technique specifically suited to guarantee the processor’s correct behavior during the operative lifetime, as mandated by functional safety standards such as ISO26262. Developing STLs for stuck-at faults requires significant manual efforts from test engineers, and targeting delay faults is even more challenging. In order to support this process, in this paper we propose a method to automate the creation of STLs targeting delay faults starting from existing STLs targeting stuck-at faults. The method is based first on identifying excited but not-observed transition delay faults and then adding suitable instructions able to detect them. Experimental results on a RISC-V processor show that the method can systematically detect a significant percentage of the target faults with reasonable computational effort and test code size increase.

Constraint-Based Automatic SBST Generation for RISC-V Processor Families

Abstract: Software-Based Self-Tests (SBST) allow at-speed, native online-testing of processors by running software programs on the processor core, requiring no Design for Testability (DfT) infrastructure. The creation of such SBST programs often requires time-consuming manual labour that is expensive and requires in-depth knowledge of the processor’s architecture to target hard-to-test faults. In contrast, encoding the SBST generation task as a Bounded Model Checking (BMC) problem allows using sophisticated, state-of-the-art BMC solvers to automatically generate an SBST. Constraints for the BMC problem are encoded in a circuit called Validity Checker Module (VCM) and applied during SBST generation.In this paper, we focus on presenting a VCM architecture and a constraint set that allows building SBSTs that make minimal assumptions about the firmware, targeting hard-to-test faults in the ALU and register file of multiple scalar, in-order RISC-V processor families. The VCM architecture consists of a processor-specific mapping layer and a generic constraint set connected via a well-defined interface. The generic constraint set enforces the desired SBST behaviour, including controlling the processor’s pipeline state, memory accesses, and with that executed instructions, register state, and fault propagations. Using a generic constraint set allows for rapid SBST generation targeting new RISC-V processor families while keeping the generic constraints untouched. Lastly, we evaluate this approach on two RISC-V processor families, namely the DarkRISCV and a proprietary, industrial core showing the portability and strength of the approach, allowing for rapidly targeting new processors.

Multiobjective evolutionary algorithms: classifications, analyses, and new innovations

Abstract: : This research organizes, presents, and analyzes contemporary Multiobjective Evolutionary Algorithm (MOEA) research and associated Multiobjective Optimization Problems (MOPs). Using a consistent MOEA terminology and notation, each cited MOEAs' key factors are presented in tabular form for ease of MOEA identification and selection. A detailed quantitative and qualitative MOEA analysis is presented, providing a basis for conclusions about various MOEA-related issues. The traditional notion of building blocks is extended to the MOP domain in an effort to develop more effective and efficient MOEAs. Additionally, the MOEA community's limited test suites contain various functions whose origins and rationale for use are often unknown. Thus, using general test suite guidelines appropriate MOEA test function suites are substantiated and generated. An experimental methodology incorporating a solution database and appropriate metrics is offered as a proposed evaluation framework allowing absolute comparisons of specific MOEA approaches. Taken together, this document's classifications, analyses, and new innovations present a complete, contemporary view of current MOEA "state of the art" and possible future research. Researchers with basic EA knowledge may also use part of it as a largely self-contained introduction to MOEAs.

Algorithms for VLSI Physical Design Automation

Abstract: From the Publisher: This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

Genetic Algorithms for the Travelling Salesman Problem: A Review of Representations and Operators

Abstract: This paper is the result of a literature study carried out by the authors. It is a review of the different attempts made to solve the Travelling Salesman Problem with Genetic Algorithms. We present crossover and mutation operators, developed to tackle the Travelling Salesman Problem with Genetic Algorithms with different representations such as: binary representation, path representation, adjacency representation, ordinal representation and matrix representation. Likewise, we show the experimental results obtained with different standard examples using combination of crossover and mutation operators in relation with path representation.

A Taxonomy of Hybrid Metaheuristics

Abstract: Hybrid metaheuristics have received considerable interest these recent years in the field of combinatorial optimization. A wide variety of hybrid approaches have been proposed in the literature. In this paper, a taxonomy of hybrid metaheuristics is presented in an attempt to provide a common terminology and classification mechanisms. The taxonomy, while presented in terms of metaheuristics, is also applicable to most types of heuristics and exact optimization algorithms. As an illustration of the usefulness of the taxonomy an annoted bibliography is given which classifies a large number of hybrid approaches according to the taxonomy.

Interpolation and SAT-based model checking

Abstract: We consider a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants. In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.