Maurizio Martina

TL;DR: This work aims at providing an up-to-date survey, especially covering the prominent works from the last 3 years of the hardware architectures research for DNNs, covering the latest techniques in the field of dataflow, reconfigurability, variable bit-width, and sparsity.

TL;DR: A VLSI architecture is proposed for the IWT implementation, capable of achieving very high frame rates with moderate gate complexity and the effects of finite precision representation of the lifting coefficients on the compression performance are analyzed.

TL;DR: This work summarizes and compares the works for four leading platforms for the execution of algorithms such as CPU, GPU, FPGA and ASIC describing the main solutions of the state-of-the-art, giving much prominence to the last two solutions since they offer greater design flexibility and bear the potential of high energy-efficiency, especially for the inference process.

TL;DR: The hardware architectures of typical IoT devices are presented and many of the low power techniques which make them appealing for a large scale of applications are summed up.

TL;DR: This brief proposes a multiplierless VLSI architecture for the famous 9/7 wavelet filters with the possibility to compute the 5/3 wavelet results into the9/7 data path with a reduced number of adders compared to other solutions.