Meenakshi Bansal

Bio: Meenakshi Bansal is an academic researcher from Chitkara University. The author has contributed to research in topics: Airflow & Low voltage. The author has an hindex of 3, co-authored 7 publications receiving 32 citations.

SSTL I/O Standard based environment friendly energyl efficient ROM design on FPGA

Abstract: Stub Series Terminated Logic (SSTL) is an Input/output standard. It is used to match the impedance of line, port and device of our design under consideration. Therefore, selection of energy efficient SSTL I/O standard among available different class of SSTL logic family in FPGA, plays a vital role to achieve energy efficiency in design under test (DUT). Here, DUT is ROM. ROM is an integral part of processor. Therefore, energy efficient design of RAM is a building block of energy efficient processor. We are using Verilog hardware description language, Virtex-6 FPGA, and Xilinx ISE simulator. We are operating ROM with the highest operating frequency of 4th generation i7 processor to test the compatibility of this design with the latest hardware in use. When there is no demand of peak performance, then we can save 74.5% clock power, 75% signal power, and 30.83% I/O power by operating our device with 1GHz frequency in place of 4GHz. There is no change in clock power and signal power but SSTL2_H_DCI having 80.24% 83.38% 62.92% and 76.52% and 83.03% more I/O power consumption with respect to SSTL2_I, SST18_I, SSTL2_I_DCI, SSTL2_II, and SSTL15 respectively at 3.3GHz.

FPGA Based Low Power ROM Design Using Capacitance Scaling

Abstract: An ideal capacitor will not dissipate any power, but a real capacitor will have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM with frequencies (2.9GHz, 3.3GHz, 3.6GHz, 3.8GHz and 4.0GHz) supported by i7 processor.By using different capacitance there comes is reduction in I/O Power and Total power but not in other Powers like Clock, and Leakage (almost negligible). When capacitance goes from 30pF to 5pF, there is a saving of 28.12% occur in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog.

LVCMOS I/O standard based environment friendly low power ROM design on FPGA

Abstract: LVCMOS is Low Voltage Complementary Metal Oxide Semiconductor. I/O standard is used to match the impedance of input line, output line, input port, output port and device in order to avoid transmission line reflection. Selection of energy efficient I/O standard is required to make energy efficient ROM. LVCMOS12 is the most optimal IO standard. Whereas, LVCMOS33 is the highest power consumer IO standard. With uniform frequency, there is no change in clock power and signal power but LVCMOS33 having 76.47%, 64.47%, 55.88%, 14.07% more I/O power consumption with respect to LVCMOS12, LVCMOS15, LVCMOS18, LVCMOS25, respectively. We can save up to 77% power using the energy efficient LVCMOS12 I/O standards. When, there is no demand of peak performance, then we can save 92.18% clock power, 100% signal power, and 75.75% I/O power by operating our device with 1GHz frequency in place of 4GHz using dynamic frequency scaling as power management techniques.

Low Power High Performance ROM Design on FPGA Using LVDCI I/O Standard

Abstract: In this work, we are using LVDCI I/O standard in energy efficient ROM design on FPGA. There is a 92% reduction in clock power, 50% reduction in signal power, 32-46% reduction in IO's power, and 25-27% reduction in total power, when we scale down frequency from 4.0GHz to 1.0GHz. There is no reduction in clock power and signal power, when we change I/O standard from LVDCI 25 to LVDCI 15, but there is reduction of 61-69% of IO's power and reduction of 16-18% in total power. This design is implemented on Virtex-5 FPGA using Verilog hardware description language and Xilinx ISE simulator. LVDCI 15, LVDCI 18, LVDCI 25, HSLVDCI 15 and HSLVDCI 18 are five different IO standard is in use to design energy efficient ROM. LV stands for Low Voltage, HS means High Speed and DCI means Digitally Control impedance.

HSTL I/O standard based environment friendly energy efficient ROM design on FPGA

Abstract: In order to extend the battery life and gain in term of portability, there is always a research gap in low power processor design. In order to complete low power processor design project, there is need to re-design each and every part of processor with low power techniques. Selection of energy efficient I/O standard is also playing a significant role in energy efficient design. In this work, we are using High Speed Transceiver Logic (HSTL) in energy efficient ROM design on Virtex-5 FPGA using Verilog hardware description language and Xilinx ISE simulator. Here, we use six different HSTL IO Standards. These are: HSTL_I, HSTL_II, HSTL_III, HSTL_III_18, HSTL_III_DCI, and HSTL_II_18. For each IO standard, we are going to run our ROM design with 1.0GHz, 2.9GHz, 3.3GHz, 3.6GHz, 3.8GHz and 4.0GHz device operating frequency. With dynamic frequency scaling, we are saving 92.18% clock power, 100% signal power, and 9.82% I/O power by operating our device with 1GHz frequency in place of 4GHz. There is no change in clock power and signal power but HSTL_III_DCI having 39.06%, 9.21%, 25.88%, 25.88%, 9.21% more I/O power consumption with respect to HSTL_I, HSTL_II, HSTL_III, HSTL_III_18, HSTL_II_18 respectively at 3.3GHz frequency.

VLSI Implementation of Green Computing Control Unit on Zynq FPGA for Green Communication

Abstract: The issue of the energy shortage is affecting the entire planet. This is occurring because of massive population and industry growth around the world. As a result, the entire world is attempting to implement green networking systems and manufacture the power/energy efficient products. This research work discusses the green networking system technologies. This work introduces a power-efficient control unit (CU) design and implemented on the Zynq SoC (System on Chip) ultrascale field programmable gate array (FPGA). The VIVADO HLx Design Suite is used to simulate and analyze the CU model which is considered as one of the key components of central processing unit (CPU), used for data communication purposes. The CU is made suitable for the green communication by making it power-efficient. Therefore, the power consumption of the CU is analyzed for the various set frequency value ranging between 100 MHz and 5 GHz, and it is discovered that as the clock frequency rises up, the total power consumption also tends to get increased. The total power of the proposed model is reduced by 77.42%, 21.29%, and 17.93% from three models, respectively, being compared in the present paper. Final results shows that the CU is better suited to run at low frequencies to optimize power consumption.

Scaling of Output Load in Energy Efficient FIR Filter for Green Communication on Ultra-Scale FPGA

Abstract: FIR Filter always remains in linear phase with the help of symmetric coefficient. This feature makes it ideal for phase-sensitive applications like data communications. Design of FIR filter with energy efficiency makes excellent sense to achieve energy efficiency in digital selected frequency module of communication. We are using scaling of output load from 5000 to 0 pF to show an effect of output load on both on-chip and off-chip power consumption of FIR filter design. 20 nm technology based FVA1156 package and Kintex-7 family ultra-scale FPGA is taken under reconsideration for implementation of our model. With the use of HSTL_II IO standards, there is 84.39 and 92.83% reduction in IOs power when we scale down capacitance from 5000 to 500 and 0 pF respectively. With the use of HSTL_I_18 IO standards, there is 72.48 and 80.13% reduction in total on-chip power when we scale down capacitance from 5000 to 500 and 0 pF respectively. Along with IOs power and total on-chip power, we have also analyzed Off-chip device power, junction temperature, thermal margin, and different dynamic power likes Signal power, logic power, and DSP power.

Designing of Power Efficient ROM Using LVTTL and Mobile-DDR IO Standard on 28nm FPGA

Abstract: This paper contains designing of energy efficient memory circuit using two different IO standard i.e. LVTTL and Mobile-DDR on 28nm (Artix-7) Field Programmable Gate Array. We are using Xilinx ISE simulator version 14.2, Verilog hardware description language and Artix-7 FPGA. The design has been tested at different operating frequencies of Latest Intel processor that are at Intel I-3, Intel I-5 and Intel I-7 to check the compatibility of the design with processors available in the market and to find most efficient IO standard at different operating frequencies.

HSTL IO Standards Based Processor Specific Green Counter Design on 90nm FPGAAbhay Saxena

Abstract: Extending battery life and increase in portability of modern electronic devices and gadgets are the main motives behind the Green Computing which is also known by similar terms like energy efficient design or low power design or green design. Such efficiency is only possible if all the components of processor are also energy efficient. In this work, the researchers tried to analyze the energy optimization possibility in counter design by selection of energy efficient IO standards. The researchers had used High Speed Transceiver Logic for the purpose of energy efficient counter design on Spartan3 (90nm) FPGA (field-programmable gate array) using VHDL (VHSIC Hardware Description Language) hardware description language along with the Xilinx ISE simulator for the analysis and synthesis of counters. Spartan 3 with 90 nm low power is used to achieve substantial power savings. Here, researchers have used five different HSTL IO standards for this work. The standards used are HSTL_I, HSTL_III, HSTL_III_18, HSTL_III_DCI and HSTL_II_18. With these sets of IO standards, Researchers had run their counter design on various device operating frequencies (1.0 GHz to 4.0 GHz). The results clearly indicate that this dynamic frequency (1.0 GHz in lieu of 4.0 GHz) scaling had saved 45% of total power.

Capacitance Scaling With Different IO Standard Based Energy Efficient Bio-Medical Wrist Watch Design on 28nm FGPA

Abstract: In this paper, we have designed an energy efficient wrist watch on 28nm FPGA. The code has been implemented in Xilinx ISE Design Suite 14.2. The device used is XC7K160T, package used is FBG676 and it is working on -3 speed grade. The wrist band will take the blood pressure as input and will tell about the state of the person wearing it. The design supports Internet of things service that’s why IP addresses are involved. This wrist band design is very helpful in biomedical areas. Research is in progress in this field. In this paper frequency is varied to obtain power consumption of Wrist Watch. Airflow has been kept 250 LFM and medium Heat sink. IO Standards has been varied in order to achieve an energy efficient device. Main emphasis has been done on MOBILE_DDR, LVTTL, HSUL_12, HSTL_I, LVCMOS33 and SSTL15 IO Standards. To design an energy efficient device we are using capacitance scaling and the capacitance is scaled down from 100pF to 20pF. During capacitance scaling, we observe that there is no change in clock power, logic power and signal power. Thermal Aware design is current research area. Analysis has been at two temperatures that is at 25 degree Celsius and at 50 degree Celsius. At the end we can conclude that the maximum power is consumed at 2.2GHz and minimum power is consumed at 1.2GHz. In respect of capacitance maximum power is consumed at 100pF and minimum power is consumed at 20pF at both temperatures at 25 degree Celsius and 50 degree Celsius.