Mehdi Ehsanian

Bio: Mehdi Ehsanian is an academic researcher from K.N.Toosi University of Technology. The author has contributed to research in topics: CMOS & Jitter. The author has an hindex of 5, co-authored 31 publications receiving 102 citations. Previous affiliations of Mehdi Ehsanian include Intel & Université de Montréal.

An Improved KFCM Clustering Method Used for Multiple Fault Diagnosis of Analog Circuits

Abstract: This study presents a new method for multiple fault diagnosis in moderate-sized analog circuits. Based on this method, a classifier is independently designed for each of the circuit components. Each of these classifiers only classifies the defect modes associated with the related component. The resultant effect is the much lower number of fault classes in each classifier than all of the circuit faults. Classifiers are designed based on a two-stage clustering method. Firstly, whole data are clustered by using Kmeans algorithm. Then, samples in each cluster are classified using a new version of KFCM algorithm. In this algorithm, initial cluster centers, as well as their number, are estimated by using an efficient method. Comparison with a neural network shows its very lower accuracy in classifying large number multiple faults. However, the proposed technique is capable of diagnosing multiple faults with acceptable accuracy (more than 91% for 15 single faults and more than 60% for most of the other multiple faults with the number greater than 200). Also this method has higher accuracy than traditional KFCM and YKFCM algorithms and this superiority rises along with increase in the number of faults.

A new digital test approach for analog-to-digital converter testing

Abstract: A fully digital built-in self-test (BIST) for analog-to-digital converters is presented in this paper. This test circuit is capable of measuring the DNL, INL, offset error and gain error, and mainly consists of several registers and some digital subtracters. The main advantage of this BIST is the ability to test DNL and INL for all codes in the digital domain, which in turn eliminate the necessity of calibration. On the other hand, some parts of the analog-to-digital converter with minor modifications are used in the BIST simultaneously. This also reduces the area overhead and the cost of the test. The proposed BIST structure presents a compromise between test accuracy, area overhead and test cost. The BIST circuitry has been designed using CMOS 1.5 /spl mu/m technology. The simulation results of the test show that it can be applied to medium resolution analog-to-digital converter or high resolution pipelined analog-to-digital converter. The presented BIST shows satisfactory results for 9-bit pipelined analog-to-digital converter.

Oscillation-based Test for Measuring 1dB Gain Compression Point of Power Amplifiers

Abstract: This paper describes a new method to measure the 1dB gain compression point (PldB) for a 5.8GHz power amplifier (PA). The proposed method is based on oscillation built-in self-test (OBIST) method. The circuit is designed in 180nm CMOS technology. The PA is transformed into an oscillator and growing PA input amplitude is produced without an external signal generator. This technique offers a proper growth rate of the PA input voltage amplitude with a proper operating frequency. Using this method, PldB occurs when the voltage input amplitude is 460.5mV. Finally, the new quasi OBIST method can measure the voltage input amplitude where the PldB occur with approximately 2% error.

A 0.9-V supply, 16.2 nW, fully MOSFET resistorless bandgap reference using sub-threshold operation

Abstract: A nano-watt bandgap voltage reference (BGR) is presented. To provide a low-voltage and low-power BGR, the circuit has been biased in the sub-threshold region; thereby, drawing a few nano-amperes current from the source, has been achieved. In order to reduce die area and also power consumption, instead of resistor, transistor is used. To generate PTAT voltage, self-cascode composite structure is used for the transistors. The results from post-layout simulation using 0.18-μm standard CMOS technology show that the proposed BGR circuit generates a reference voltage of 625 mV, obtaining temperature coefficient of 13 ppm/ °C in the temperature range of − 25 °C to 110 °C. The simulated power supply rejection ratio is 42 dB. Fully designed with MOS transistors, the circuit draws 18 nA from a 0.9-V supply. The active area of the proposed BGR is 0.00067 mm2.

Use of embedded sensors for built-in-test RF circuits

Abstract: Testing of on-chip RF and microwave circuits has always been a challenge to test engineers and has been more so in the recent past due to the high signal frequencies involved and the dense levels of circuit integration. In this paper, we propose to embed low-cost sensors into RF signal paths for the purpose of built-in test. The sensor characteristics are chosen in such a way that the sensor outputs, which are low frequency or DC signals, are tightly correlated with the target test specification values of the RF device-under-test. Hence, instead of testing the devices specifically for complex performance metrics (this is difficult for embedded circuits), the outputs of the sensors are used to accurately estimate the target test specification values when the device-under-test is stimulated with sinusoidal stimulus. This significantly impacts the cost of manufacturing test and allows testing to be performed using low-cost external testers. Using this method, the target test specification values can be estimated with an accuracy of /spl plusmn/5% of their actual value.

Ultra-low power bias current generation and utilization in current and voltage source and regulator devices

Abstract: A bias current topology with embodiments in current source, current reference, (pseudo bandgap) voltage reference, and bandgap voltage reference that operate at ultra low currents and low power supply voltages which may use main stream standard digital Complementary Metal-Oxide-Semiconductor (CMOS) processes. The bias current topology uses chiefly a self cascode (SC), whose active resistor MOSFET is paced in series with the gate input of the MOSFETs that help generate the proportional to absolute temperature (PTAT) voltage that is applied to the active resistor MOSFET to produce a bias current.

Code-width testing-based compact ADC BIST circuit

Abstract: This paper proposes a new analog-to-digital converter (ADC) built-in self-test (BIST) scheme based on code-width and sample-difference testing that does not require a slope-calibrated ramp signal. The proposed BIST scheme can be implemented by a simple digital circuit whose gate count is only approximately 550. The proposed BIST scheme is verified by simulation with 138 test circuits of 6-b pipeline ADC with arbitrary faults. Simulation results show that it effectively detects not only the catastrophic faults but also some parametric faults. The simulated fault coverage is approximately 99%.

All-digital TX frequency synthesizer and discrete-time receiver for bluetooth radio in 130-nm CMOS

Abstract: We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm 2 and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.