M
Mehmet Rasit Yuce
Researcher at Monash University
Publications - 264
Citations - 6598
Mehmet Rasit Yuce is an academic researcher from Monash University. The author has contributed to research in topics: Body area network & Wireless sensor network. The author has an hindex of 38, co-authored 255 publications receiving 5049 citations. Previous affiliations of Mehmet Rasit Yuce include University of California, Santa Cruz & Griffith University.
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Journal ArticleDOI
A 128-Channel 6 mW Wireless Neural Recording IC With Spike Feature Extraction and UWB Transmitter
TL;DR: A 128-channel neural recording integrated circuit with on-the-fly spike feature extraction and wireless telemetry with computationally efficient spike detection and feature extraction algorithms attribute to an auspicious DSP implementation on-chip.
Journal ArticleDOI
Implementation of wireless body area networks for healthcare systems
TL;DR: This work describes the implementation of a complete wireless body-area network (WBAN) system to deploy in medical environments and a WBAN system that has been designed for healthcare applications will be presented in detail herein.
Journal ArticleDOI
An Autonomous Wireless Body Area Network Implementation Towards IoT Connected Healthcare Applications
TL;DR: The proposed system with solar energy harvesting demonstrates that long-term continuous medical monitoring based on WBAN is possible provided that the subject stays outside for a short period of time in a day.
Journal ArticleDOI
An Internet-of-Things (IoT) Network System for Connected Safety and Health Monitoring Applications
TL;DR: A hybrid wearable sensor network system towards the Internet of Things (IoT) connected safety and health monitoring applications aimed at improving safety in the outdoor workplace is presented.
Proceedings ArticleDOI
A 128-Channel 6mW Wireless Neural Recording IC with On-the-Fly Spike Sorting and UWB Tansmitter
Moo-Sung Chae,Wentai Liu,Zhi Yang,Tung-Chien Chen,Jungsuk Kim,Mohanasankar Sivaprakasam,Mehmet Rasit Yuce +6 more
TL;DR: The chip is composed of eight 16-channel front-end blocks, data serializing circuits, a DSP for on-chip spike sorting, digital MUX, encoder, UWB TX, and bias generators.