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Menbere Kina Tekleyohannes

Bio: Menbere Kina Tekleyohannes is an academic researcher from Kaiserslautern University of Technology. The author has contributed to research in topics: Historical document & Optical character recognition. The author has an hindex of 2, co-authored 5 publications receiving 19 citations.

Papers
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Proceedings ArticleDOI
21 May 2018
TL;DR: A dedicated IP block, configurable for different morphological operations, size and origin of structuring elements, optimized for low power, small resource consumption and high throughput for the application in an industry 4.0 environment is presented.
Abstract: For many years, morphological operations have been widely used as image processing techniques for various applications. However, the rapidly growing computational complexity due to processing of large structuring elements for high resolution images, challenges the limits of conventional processing platforms. Nowadays, hybrid field programmable gate arrays (FPGAs) have shown a promising approach for such high performance applications. These devices have compelling advantages over traditional platforms due to their low power consumption and high-customization. However, the efficiency comes at the cost of loss in flexibility and adaptability compared to software solutions. Moreover, morphological operations require significant memory resources. In this paper, we present a dedicated IP block, configurable for different morphological operations, size and origin of structuring elements. This IP core is optimized for low power, small resource consumption and high throughput for the application in an industry 4.0 environment. Furthermore, the image size and radiometric resolutions can be configured to meet the requirements of flexibility. Our new architecture achieves a high throughput comparable to the state-of-the-art, while providing a high flexibility.

9 citations

Proceedings ArticleDOI
27 Mar 2017
TL;DR: This paper proposes a hybrid software-hardware architecture of CCA for an industrial application using Xilinx Zynq-7000 All Programmable System on Chip (SoC), and offloading the most resource consuming part of the algorithm to the embedded CPU achieves high performance, while reducing the required resources on the FPGA.
Abstract: In recent years, connected component analysis (CCA) has become one of the vital image/video processing algorithms due to its wide-range applicability in the field of computer vision. Numerous applications such as pattern recognition, object detection and image segmentation involve connected component analysis. In the context of camera-based inspection systems, CCA plays an important role for quality assurance. State-of-the-art hardware architectures offer high performance implementations of CCA using field programmable gate arrays (FPGAs). However, due to their high memory-demand, most of these implementations inhibit a large resource utilization. In this paper, we propose a hybrid software-hardware architecture of CCA for an industrial application using Xilinx Zynq-7000 All Programmable System on Chip (SoC). By offloading the most resource consuming part of the algorithm to the embedded CPU, we achieved high performance, while reducing the required resources on the FPGA. Our proposed architecture saves more than 30% of on-chip memory (Block RAMs) compared to state-of-the-art hardware architectures without affecting the throughput. Furthermore, due to the embedded CPU, our system provides a versatile and highly flexible feature extraction at run-time without the necessity to reconfigure the FPGA.

9 citations

Journal ArticleDOI
TL;DR: In this paper, the authors proposed a low power energy-efficient accelerator with real-time capabilities called iDocChip, which is a configurable hybrid hardware-software programmable system-on-chip (SoC) based anyOCR for digitizing historical documents.
Abstract: In recent years, $$\hbox {optical character recognition (OCR)}$$ systems have been used to digitally preserve historical archives. To transcribe historical archives into a machine-readable form, first, the documents are scanned, then an $$\hbox {OCR}$$ is applied. In order to digitize documents without the need to remove them from where they are archived, it is valuable to have a portable device that combines scanning and $$\hbox {OCR}$$ capabilities. Nowadays, there exist many commercial and open-source document digitization techniques, which are optimized for contemporary documents. However, they fail to give sufficient text recognition accuracy for transcribing historical documents due to the severe quality degradation of such documents. On the contrary, the anyOCR system, which is designed to mainly digitize historical documents, provides high accuracy. However, this comes at a cost of high computational complexity resulting in long runtime and high power consumption. To tackle these challenges, we propose a low power energy-efficient accelerator with real-time capabilities called iDocChip, which is a configurable hybrid hardware-software programmable $$\hbox {System-on-Chip (SoC)}$$ based on anyOCR for digitizing historical documents. In this paper, we focus on one of the most crucial processing steps in the anyOCR system: Text and Image Segmentation, which makes use of a multi-resolution morphology-based algorithm. Moreover, an optimized $$\hbox {FPGA}$$ -based hybrid architecture of this anyOCR step along with its optimized software implementations are presented. We demonstrate our results on multiple embedded and general-purpose platforms with respect to runtime and power consumption. The resulting hardware accelerator outperforms the existing anyOCR by 6.2 $$\times$$ , while achieving 207 $$\times$$ higher energy-efficiency and maintaining its high accuracy.

3 citations

Proceedings ArticleDOI
01 Dec 2019
TL;DR: iDocChip is a low power, energy-efficient accelerator with real-time capabilities called iDocChip, which is a hybrid hardware-software programmable System-on-Chip (SoC) for digitizing historical documents, and the resulting custom hardware accelerator outperforms the existing anyOCR software implementation by 120x, while achieving 1700x higher energy efficiency without affecting the high accuracy of the system.
Abstract: Digitizing historical archives poses a great challenge due to the quality degradation existing in these documents. Hence, even well-established Optical Character Recognition (OCR) systems, such as Abby, OCRopus, Tesseract, etc., fail to give sufficient recognition accuracy for historical archives, since they are optimized for transcribing contemporary documents. In contrast, the open-source anyOCR system is designed specifically for digitizing historical documents with state-of-the-art image processing techniques, to achieve high accuracy. Nowadays, the retrieval of historical document images for further OCR requires special scanning devices that are bulky and stationary. As a result, a portable device that combines scanning and OCR capabilities is beneficial to transcribe documents without the need to remove them from where they are archived. For example, smart goggles equipped with embedded OCR device can be used for instant word spotting. However, the available anyOCR software implementation has long runtime and high power consumption. As a solution, we propose a low power, energy-efficient accelerator with real-time capabilities called iDocChip, which is a hybrid hardware-software programmable System-on-Chip (SoC) for digitizing historical documents. This chip can be easily integrated in a portable device. This paper focuses on one of the most crucial processing steps in anyOCR: Text line extraction. We propose, to the best of our knowledge, the first hybrid hardware-software architecture of the text line extraction technique implemented on an FPGA based programmable SoC. The resulting custom hardware accelerator outperforms the existing anyOCR software implementation by 120x, while achieving 1700x higher energy efficiency without affecting the high accuracy of the system.

2 citations

Journal ArticleDOI
TL;DR: In this article, a configurable hardware-software programmable SoC called iDocChip that makes use of anyOCR techniques to achieve high accuracy was designed and implemented for portable devices that combine scanning and OCR capabilities.
Abstract: In recent years, there has been an increasing demand to digitize and electronically access historical records. Optical character recognition (OCR) is typically applied to scanned historical archives to transcribe them from document images into machine-readable texts. Many libraries offer special stationary equipment for scanning historical documents. However, to digitize these records without removing them from where they are archived, portable devices that combine scanning and OCR capabilities are required. An existing end-to-end OCR software called anyOCR achieves high recognition accuracy for historical documents. However, it is unsuitable for portable devices, as it exhibits high computational complexity resulting in long runtime and high power consumption. Therefore, we have designed and implemented a configurable hardware-software programmable SoC called iDocChip that makes use of anyOCR techniques to achieve high accuracy. As a low-power and energy-efficient system with real-time capabilities, the iDocChip delivers the required portability. In this paper, we present the hybrid CPU-FPGA architecture of iDocChip along with the optimized software implementations of the anyOCR. We demonstrate our results on multiple platforms with respect to runtime and power consumption. The iDocChip system outperforms the existing anyOCR by 44× while achieving 2201× higher energy efficiency and a 3.8% increase in recognition accuracy.

Cited by
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Journal ArticleDOI
TL;DR: This paper aims to review various methodologies used and how it has evolved to give better results in the past years, closely moving towards usage of machine learning.
Abstract: Vehicle detection and classification has been an area of application of image processing and machine learning which is being researched extensively in accordance with its importance due to increasing number of vehicles, traffic rule defaulters and accidents. This paper aims to review various methodologies used and how it has evolved to give better results in the past years, closely moving towards usage of machine learning. This has resulted in advancing the problem statement towards helmet detection followed by number plate detection of defaulters. Object detection and Text recognition that are available in various frameworks offer built-in models which are easy to use or offer easy methods to build and train customized models.

32 citations

Proceedings ArticleDOI
03 Jul 2019
TL;DR: A method to adjust in real-time the morphological parameters to the illumination changes in the scene to be robust to illumination changes, and to significantly outperform the conventional approach is proposed.
Abstract: Object detection represents the most important component of Automated Vehicular Surveillance (AVS) systems. Moving vehicle detection based on background subtraction, with fixed morphological parameters, is a popular approach in AVS systems. However, the performance of such an approach deteriorates in the presence of sudden illumination changes in the scene. To address this issue, this paper proposes a method to adjust in real-time the morphological parameters to the illumination changes in the scene. The method is based on machine learning. The features used in the machine learning models are first, second, third and fourth-order statistics of the grayscale images, and the outputs are the appropriate morphological parameters. The resulting background subtraction-based object detection is shown to be robust to illumination changes, and to significantly outperform the conventional approach. Further, artificial neural network (ANN) is shown to provide better performance than Naive Bayes and K-Nearest Neighbours models.

13 citations

Journal Article
TL;DR: This paper presents a structuring element decomposition method and a corresponding morphological erosion algorithm able to compute the binary erosion of an image using a single regular pass whatever the size of the convexstructuring element.
Abstract: This paper presents a structuring element decomposition method and a corresponding morphological erosion algorithm able to compute the binary erosion of an image using a single regular pass whatever the size of the convex structuring element. Similarly to classical dilation-based methods [1], the proposed decomposition is iterative and builds a growing set of structuring elements. The novelty consists in using the set union instead of the Minkowski sum as the elementary structuring element construction operator. At each step of the construction, already-built elements can be joined together in any combination of translations and set unions. There is no restrictions on the shape of the structuring element that can be built. Arbitrary shape decompositions can be obtained with existing genetic algorithms [2] with an homogeneous construction method. This paper, however, addresses the problem of convex shape decomposition with a deterministic method.

12 citations

Journal ArticleDOI
TL;DR: This paper presents a novel hardware-oriented labeling approach able to process input pixels in parallel, thus speeding up the labeling task with respect to state-of-the-art competitors.
Abstract: Connected component labeling is one of the most important processes for image analysis, image understanding, pattern recognition, and computer vision. It performs inherently sequential operations to scan a binary input image and to assign a unique label to all pixels of each object. This paper presents a novel hardware-oriented labeling approach able to process input pixels in parallel, thus speeding up the labeling task with respect to state-of-the-art competitors. For purposes of comparison with existing designs, several hardware implementations are characterized for different image sizes and realization platforms. The obtained results demonstrate that frame rates and resource efficiency significantly higher than existing counterparts are achieved. The proposed hardware architecture is purposely designed to comply with the fourth generation of the advanced extensible interface (AXI4) protocol and to store intermediate and final outputs within an off-chip memory. Therefore, it can be directly integrated as a custom accelerator in virtually any modern heterogeneous embedded system-on-chip (SoC). As an example, when integrated within the Xilinx Zynq-7000 X C7Z020 SoC, the novel design processes more than 1.9 pixels per clock cycle, thus furnishing more than 30 2k × 2k labeled frames per second by using 3688 Look-Up Tables (LUTs), 1415 Flip Flops (FFs), and 10 kb of on-chip memory.

9 citations

Journal ArticleDOI
TL;DR: A novel algorithm is presented which integrates the classic template matching approach with an efficient angle estimation method, so that the rotation and location of the IC chip can be identified precisely.
Abstract: This paper presents the system and algorithm designs of a real-time automated integrated circuit (IC) marking inspection system based on the embedded platform. Specifically, the system-level design and the integration of hardware and software components are illustrated in this paper. Furthermore, in order to enhance the accuracy of IC inspection, this paper presents a novel algorithm which integrates the classic template matching approach with an efficient angle estimation method, so that the rotation and location of the IC chip can be identified precisely. Formal outline of the proposed algorithm is given in this paper. Moreover, aiming at reducing the computation time, the algorithmic optimizations based on the multi-core embedded processor and the single instruction, multiple data architecture are presented. The experiment results show that, compared to the conventional IC marking inspection algorithm, the proposed system and algorithm greatly improve the efficiency and accuracy of image processing on the embedded system. In particular, when the size of the target image is $640\times480$ pixels and size of the template image is 80 $\times $ 100, the average inspection time is 31 ms, which is an approximately $20{\times }$ improvement from the conventional inspection scheme.

8 citations