Mi-Chang Chang

Bio: Mi-Chang Chang is an academic researcher. The author has contributed to research in topics: NMOS logic & Electrostatic discharge. The author has an hindex of 3, co-authored 3 publications receiving 236 citations.

Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations

Abstract: A circuit-level simulator for ESD and EOS is presented. Equations for modeling the high current behavior of NMOS and PMOS transistors have been developed and implemented in SPICE. A simple and practical extraction methodology for obtaining the bipolar parameters is given, which uses the three terminal currents obtained from a single high current I-V curve. Simulation results are presented and compared to experimental data for single devices as well as a practical output circuit.

Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high-current simulations

Abstract: The design and optimization of ESD protection circuits is greatly enhanced by the ability to perform circuit-level simulations of the protection circuits and the I/O buffers. Most available simulators do not cover the high current region of the circuit operation, but still enable an approximate analysis to be made of the behaviour under ESD conditions. In this article, a description of the behaviour of the MOS device in the high current regime is presented together with the model equations governing that behaviour. The equations have been implemented into a SPICE circuit simulator, and the experimental and simulation results are given. A simple parameter extraction methodology is presented that uses the terminal currents from a single MOS DC I-V curve to obtain all the MOS and bipolar parameters required for the model.

A unified substrate current model for weak and strong impact ionization in sub-0.25 /spl mu/m NMOS devices

Abstract: We have developed a new unified substrate current model for weak and strong impact-ionization The model which is semi-empirical is able to capture non-local field effects The importance of this model is its simplicity requiring three parameters which can be extracted easily from a single wafer-level measurement The implementation of this model in a circuit simulator provides the capability to include hot-carrier and ESD effects into circuit design optimization, which is essential for achieving design-in-reliability targets

Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits

Abstract: An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented The history and evolution of SCR device used for on-chip ESD protection is introduced Moreover, two practical problems (higher switching voltage and transient-induced latchup issue) limiting the use of SCR-based devices in on-chip ESD protection are reported Some modified device structures and trigger-assist circuit techniques to reduce the switching voltage of SCR-based devices are discussed The solutions to overcome latchup issue in the SCR-based devices are also discussed to safely apply the SCR-based devices for on-chip ESD protection in CMOS IC products

The state of the art of electrostatic discharge protection: physics, technology, circuits, design, simulation, and scaling

Abstract: This paper discusses state-of-the-art electrostatic discharge (ESD) protection in advanced semiconductor technologies and emerging technologies. ESD physics, semiconductor process issues, device and circuit simulation, circuits, and devices are examined.

Substrate pump NMOS for ESD protection applications

Abstract: The use of a substrate pump to achieve uniform npn protection in a multi-finger NMOS is reported for advanced CMOS technologies with silicide. The novel feature of this device technique is the implementation of a floating guardring to effectively pump the local substrate of the protection NMOS. SPICE simulations are presented to illustrate the device concept as well as the device design optimization.

Design methodology and optimization of gate-driven NMOS ESD protection circuits in submicron CMOS processes

Abstract: This paper describes the design methodology for gate driven NMOS ESD protection in submicron CMOS processes. A new PNP Driven NMOS (PDNMOS)-protection scheme is presented. Without requiring any additional process steps or introducing any additional impedance in signal path, the PDN-MOS is effective even for small analog/mixed-signal designs. SPICE simulations are used to optimize the design. High ESD performance of the PDNMOS protection in both nonsilicided and silicided submicron processes is demonstrated in this work.

Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high-current simulations

Abstract: The design and optimization of ESD protection circuits is greatly enhanced by the ability to perform circuit-level simulations of the protection circuits and the I/O buffers. Most available simulators do not cover the high current region of the circuit operation, but still enable an approximate analysis to be made of the behaviour under ESD conditions. In this article, a description of the behaviour of the MOS device in the high current regime is presented together with the model equations governing that behaviour. The equations have been implemented into a SPICE circuit simulator, and the experimental and simulation results are given. A simple parameter extraction methodology is presented that uses the terminal currents from a single MOS DC I-V curve to obtain all the MOS and bipolar parameters required for the model.