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Author

Michael Sanie

Bio: Michael Sanie is an academic researcher. The author has contributed to research in topics: Integrated circuit layout & Systems design. The author has an hindex of 2, co-authored 2 publications receiving 39 citations.

Papers
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Proceedings ArticleDOI
22 Jun 2001
TL;DR: This paper presents a methodology targeted for standard-cell or structured-custom design styles that start from standard-cells created in a manner in which all issues regarding generation of AltPSM are effectively considered, and are then used in a typical cell-based (synthesis-automatic place and route) flow to produce design layouts that are ready for cost-effective silicon manufacturing.
Abstract: As the semiconductor industry enters the subwavelength era where silicon features are much smaller that the wavelength of the light used to create them, a number of “subwavelength” technologies such as Optical Proximity Correction (OPC) and Phase-Shifting Masks (PSM) have been introduced to produce integrated circuits (ICs) with acceptable yields. An effective approach to subwavelength IC production includes a combination of these techniques, including OPC and PSM. Nevertheless, as we approach silicon features of 0.10&mgr and below, Alternating PSM (AltPSM) becomes a critical part of the technology portfolio needed to achieve IC requirements. An effective EDA methodology that generates AltPSM ICs must guarantee correct generation of AltPSM layouts, maintain or improve today's design productivity, and leverage existing tools and flows. The implementation of such a methodology becomes more complex as phase shifting is applied to all critical features, including those outside of transistor gates. In this paper, we present a methodology targeted for standard-cell or structured-custom design styles. We also present examples of designs that start from standard-cells created in a manner in which all issues regarding generation of AltPSM are effectively considered, and are used in a typical cell-based (synthesis-Automatic Place & Route) flow to produce design layouts that are ready for cost-effective silicon manufacturing.

34 citations

Proceedings ArticleDOI
08 Jul 2003
TL;DR: This paper presents the result of a project, collaborated by Cadence Design Systems, Numerical Technologies, DuPont Photomasks, and Nikon, aimed at optimizing each step of the lithography supply chain for the X Architecture from masks to wafers at 130 nm.
Abstract: The X Architecture is a novel on-chip interconnect architecture based on the pervasive use of diagonal wiring. This diagonal wiring reduces total chip wire length by an average 20% and via count by an average of 30%, resulting in simultaneous improvements in chip speed, power, a cost. Thirty percent or greater reduction in via counts is a compelling feature for IC design - but can chips with massive amounts of diagonal wiring be manufactured without some other penalty? This paper presents the result of a project, collaborated by Cadence Design Systems, Numerical Technologies, DuPont Photomasks, and Nikon, aimed at optimizing each step of the lithography supply chain for the Architecture from masks to wafers at 130 nm.

5 citations


Cited by
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Journal Article
TL;DR: The phase-shifting mask as mentioned in this paper consists of a normal transmission mask that has been coated with a transparent layer patterned to ensure that the optical phases of nearest apertures are opposite.
Abstract: The phase-shifting mask consists of a normal transmission mask that has been coated with a transparent layer patterned to ensure that the optical phases of nearest apertures are opposite. Destructive interference between waves from adjacent apertures cancels some diffraction effects and increases the spatial resolution with which such patterns can be projected. A simple theory predicts a near doubling of resolution for illumination with partial incoherence σ < 0.3, and substantial improvements in resolution for σ < 0.7. Initial results obtained with a phase-shifting mask patterned with typical device structures by electron-beam lithography and exposed using a Mann 4800 10× tool reveals a 40-percent increase in usuable resolution with some structures printed at a resolution of 1000 lines/mm. Phase-shifting mask structures can be used to facilitate proximity printing with larger gaps between mask and wafer. Theory indicates that the increase in resolution is accompanied by a minimal decrease in depth of focus. Thus the phase-shifting mask may be the most desirable device for enhancing optical lithography resolution in the VLSI/VHSIC era.

705 citations

Patent
06 Feb 2002
TL;DR: In this paper, techniques for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features, are presented.
Abstract: Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of assist features and proximity correction features. The method includes applying an adjustment to a phase shift mask pattern including a first and a second phase shift window, and a control chrome with a control width, and/or to a trim mask pattern having a trim shape with a trim width based upon one or both of a rule based correction and a model based correction to improve a match between a resulting exposure pattern and a target feature.

241 citations

Patent
23 Sep 2002
TL;DR: In this paper, the authors proposed a method to perform optical proximity correction (OPC) during a noncritical time, e.g. early in cell library development, possibly years prior to the direct application of OPC to a final layout.
Abstract: Performing optical proximity correction (OPC) is typically done during a critical time, wherein even small delays in finishing OPC can have significant adverse effects on product introduction and/or market exposure. In accordance with one feature of the invention, sets of repeating structures in library elements and/or layout data can be identified during a noncritical time, e.g. early in cell library development, possibly years prior to the direct application of OPC to a final layout. OPC can be performed on repeating structures during this noncritical time. Later, during the critical time (e.g. during tape out), an OPC tool can use the pre-processed structures in conjunction with a chip layout to more quickly generate a modified layout, thereby saving valuable time as a chip moves from design to production.

170 citations

Patent
10 Sep 2004
TL;DR: In this article, a method for defining full phase layout for defining a layer of material in an integrated circuit is described, which can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting.
Abstract: A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.

140 citations

Patent
31 Aug 2001
TL;DR: In this article, a method and apparatus for providing correction for microloading effects is described, in which feature edges in a layout can be grouped into those edges, or edge segments, with a large edge separation, e.g. greater than n, and those having less than that separation (group A).
Abstract: A method and apparatus for providing correction for microloading effects is described. Hybrid proximity correction techniques are used to make the problem computationally more feasible. More specifically, feature edges in a layout can be grouped into those edges, or edge segments, with a large edge separation (group B), e.g. greater than n, and those having less than that separation (group A). The group B features can then be corrected for microloading effects rapidly using rules based correction. Then both groups of edges can be corrected using model based optical proximity correction using the output of the rule based correction as the ideal, or reference, layout.

140 citations