Michael Ullmann

Bio: Michael Ullmann is an academic researcher from Karlsruhe Institute of Technology. The author has contributed to research in topics: Control reconfiguration & Field-programmable gate array. The author has an hindex of 8, co-authored 15 publications receiving 422 citations.

An FPGA run-time system for dynamical on-demand reconfiguration

Abstract: Summary form only given. The handling of an increasing number of automotive comfort functionalities has become a significant problem for the most automobile manufacturers since communication, power consumption, available space and cost become important issues for a growing number of engine control units. Our contribution presents a first approach for a flexible versatile FPGA-based run-time system supporting a resource saving function multiplex.

Real-time configuration code decompression for dynamic FPGA self-reconfiguration

Abstract: Summary form only given. Xilinx Virtex FPGAs have the possibility of dynamical partial run-time reconfiguration. If a system uses this feature with many different configuration bitstreams for substitution of parts in reconfiguration memory, the amount of necessary memory increases. The sum of memory amount which has to be provided for the configuration data is not negligible. This fact suggests the investigation of compressing data before they are stored in memory modules of a system. The compressed bitstream data has to be decompressed before transferring it to the FPGA. We show an approach of compressing configuration data at design time and decompressing them with a hardware module implemented on FPGA while run-time.

On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities

Abstract: Microcontrollers and ASICs have become a dominant part during the last years in the development of embedded applications like automotive control units. As described in our previous contribution we presented an alternative approach exploiting the possibilities of partial run-time reconfiguration of state-of-the-art Xilinx Virtex FPGAs. Our approach used a run-time system software for controlling reconfiguration and message handling. This paper presents some new extensions introducing dynamic priority measures as a first approach for adaptive reconfiguration decisions.

Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems

Abstract: Current trends show that in future it will be essential that various kinds of applications are running on one chip. These require an efficient and flexible network on chip which is able to adapt to the demands of supported modules. This makes it necessary to think about what kind of network on chip will meet these requirements. This paper describes an approach for a reconfigurable network on chip which allows adapting the performance and topology at run-time to the demand of the application running on Xilinx FPGA.

Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs

Abstract: The paper describes architectural enhancements to Xilinx FPGAs that provide better support for the creation of dynamically reconfigurable designs. These are augmented by a new design methodology that uses pre-routed IP cores for communication between static and dynamic modules and permits static designs to route through regions otherwise reserved for dynamic modules. A new CAD tool flow to automate the methodology is also presented. The new tools initially target the Virtex-II, Virtex-II Pro and Virtex-4 families and are derived from Xilinx's commercial CAD tools

An FPGA run-time system for dynamical on-demand reconfiguration

Abstract: Summary form only given. The handling of an increasing number of automotive comfort functionalities has become a significant problem for the most automobile manufacturers since communication, power consumption, available space and cost become important issues for a growing number of engine control units. Our contribution presents a first approach for a flexible versatile FPGA-based run-time system supporting a resource saving function multiplex.

Context saving and restoring for multitasking in reconfigurable systems

Abstract: Today's Field Programmable Gate Arrays (FPGAs) can be reconfigured partially, which makes it possible to share resources between various functional modules (hardware tasks) over time. This concept is well known in the area of conventional operating systems. However, in order to transfer resource sharing concepts to operating systems on FPGAs, several underlying mechanisms have to be developed. One of these mechanisms is to suspend hardware tasks and restart them at another time and/or another area of the FPGA. Addressing this problem, this paper discusses ways to save and restore the state information of a hardware task. Afterwards, an implementation of a state relocation mechanisms is presented that uses the standard configuration port. In contrast to similar approaches, we significantly reduce the amount of readback data by reading only those configuration frames that contain state information. We finally determine the time overhead for task relocation, which is essential for most multitasking concepts, like defragmentation.

Dynamic and Partial FPGA Exploitation

Abstract: Today's field programmable gate array (FPGA) architectures, like Xilinx's Virtex-II series, enable partial and dynamic run-time self-reconfiguration. This feature allows the substitution of parts of a hardware design implemented on this reconfigurable hardware, and therefore, a system can be adapted to the actual demands of applications running on the chip. Exploiting this possibility enables the development of adaptive hardware for a huge variety of applications. A novel method for communication interfaces using look up table (LUT)-based communication primitives enables an exact separation of reconfigurable parts and a fast and intelligent bus-system. A new adaptive software/hardware reconfigurable system is presented in this paper, using a real application in the automotive domain implemented on a Xilinx Virtex-II 3000 FPGA to present results

Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration

Abstract: Xilinx Virtex FPGAs offer the possibility of dynamic and partial run-time reconfiguration. If a system uses this feature the designer has to take care, that no signal lines cross the border to other reconfigurable regions. Traditional solutions connecting modules on a dynamic and partial reconfigurable system use TBUF elements for connection and separation of the functional blocks. While automatically placing and routing the design, the routing-tool sometimes uses signal lines which cross the module border. The constraints given by the designer are ignored. To solve this problem, we use slices instead of TBUF elements which leads to a benefit by using an automatic modular design flow. This paper gives an overview of the used techniques and the complete system on a Xilinx XC2V3000 FPGA.