Michał Kruszewski

Bio: Michał Kruszewski is an academic researcher from Warsaw University of Technology. The author has contributed to research in topics: Emulation & Data acquisition. The author has an hindex of 2, co-authored 8 publications receiving 8 citations.

Fast Data-Driven Readout System for the Wide Aperture Silicon Tracking System of the BM@N Experiment

Abstract: The major upgrade of the BM@N experiment for the heavy ion program is a new hybrid tracking system. It consists of seven planes of GEM detectors and four silicon tracking stations based on the modules with double-sided microstrip silicon sensors of CBM type. The BM@N silicon tracking system (STS) will conceptually inherit the data acquisition system (DAQ) from the CBM silicon tracker currently in development for FAIR. This is an entirely data driven acquisition system relying on purely self-triggering readout channels, which will also be adopted for the operation with BM@N trigger. The core components of the readout chain are front-end boards (FEB), GBTxEmu board and GBTxEmu readout interface (GERI) board. The front-end board is an integrated part of the STS module. The main components of FEB are eight STS-XYTER ASICs which are needed for the readout of one side of the silicon sensor. The GBTxEmu board comprises an FPGA which emulates functionality of the CERN GBTx ASIC and provides a bidirectional optical link between front-end electronics and data processing boards in the computer nodes. The GERI board implements the following functionalities: concentrating and preprocessing of the data stream, filtering of the data according to the BM@N trigger signals and providing an interface for the detector control system (DCS) to configure readout electronics.

GBTX Emulation for BM@N/MPD Data Acquisition Systems

Abstract: The GBTX chip is widely used in high-energy experiments. However, due to export restrictions, it cannot be used in NICA. There is significant synergy in building readout chains for CBM and NICA experiments. To fully utilize this synergy, it is important to emulate the essential GBTX functionality in FPGA. For that purpose, the emulator of GBTX (GBTx- EMU) has been developed. The GBTxEMU may be implemented in cheap FPGAs, including Artix-7, and enables creating multichannel data acquisition chains based on the same front-end ASICs (SMX2 developed at AGH) as the one used in CBM. The GBTxEMU may work with the DPB boards developed for CBM, but a dedicated, price-optimized solution is under development.

Automatic management of local bus address space in complex FPGA-implemented hierarchical systems

Abstract: The FPGA-implemented data acquisition and processing systems are usually configured via local bus providing access to internal control and status registers. Management of the address space of that local bus is a well known and non-trivial problem, especially in complex hierarchical systems. Even though various solutions have been already proposed, it seems that there is still a need for an open, portable address management system, capable of operation with different local bus technologies and various control interfaces. This paper presents a proposition for such a system. The multi-level hierarchy of nested blocks with internal control and status registers is supported. The blocks and registers may be implemented as single instances or vectors of multiple instances. The structure of the system is described with the XML file. The generated address map may be stored in various formats compatible with different control interfaces (e.g., IPbus or AXI). The proposed solution is compatible with the design flow based on parametrized high-level HDL implementation of the FPGA firmware.

GBTX emulator for development and special versions of GBT-based readout chains

Abstract: The GBTX ASIC is a standard solution for providing fast control and data readout for radiation detectors used in HEP experiments. However, it is subject to export control restrictions due to the usage of radiation-hard technology. An FPGA-based GBTX emulator (GBTxEMU) has been developed to enable the development of GBT-based readout chains in countries where the original GBTX cannot be imported. Thanks to utilizing a slightly modified GBT-FGPA core, it maintains basic compatibility with standard GBT-based systems. The GBTxEMU also may be an interesting solution for developing GBT-based readout chains for less demanding experiments.

Fixed-latency system for high-speed serial transmission between FPGA devices with Forward Error Correction

Abstract: This paper presents the design of a compact pro- tocol for fixed-latency, high-speed, reliable, serial transmission between simple field-programmable gate arrays (FPGA) devices. Implementation of the project aims to delineate word boundaries, provide randomness to the electromagnetic interference (EMI) generated by the electrical transitions, allow for clock recov- ery and maintain direct current (DC) balance. An orthogonal concatenated coding scheme is used for correcting transmission errors using modified Bose–Chaudhuri–Hocquenghem (BCH) code capable of correcting all single bit errors and most of the double-adjacent errors. As a result all burst errors of a length up to 31 bits, and some of the longer group errors, are corrected within 256 bits long packet. The efficiency of the proposed solution equals 46.48%, as 119 out of 256 bits are fully available to the user. The design has been implemented and tested on Xilinx Kintex UltraScale+ KCU116 Evaluation Kit with a data rate of 28.2 Gbps. Sample latency analysis has also been performed so that user could easily carry out calculations for different transmission speed. The main advancement of the work is the use of modified BCH(15, 11) code that leads to high error correction capabilities for burst errors and user friendly packet length.

Fast Data-Driven Readout System for the Wide Aperture Silicon Tracking System of the BM@N Experiment

Abstract: The major upgrade of the BM@N experiment for the heavy ion program is a new hybrid tracking system. It consists of seven planes of GEM detectors and four silicon tracking stations based on the modules with double-sided microstrip silicon sensors of CBM type. The BM@N silicon tracking system (STS) will conceptually inherit the data acquisition system (DAQ) from the CBM silicon tracker currently in development for FAIR. This is an entirely data driven acquisition system relying on purely self-triggering readout channels, which will also be adopted for the operation with BM@N trigger. The core components of the readout chain are front-end boards (FEB), GBTxEmu board and GBTxEmu readout interface (GERI) board. The front-end board is an integrated part of the STS module. The main components of FEB are eight STS-XYTER ASICs which are needed for the readout of one side of the silicon sensor. The GBTxEmu board comprises an FPGA which emulates functionality of the CERN GBTx ASIC and provides a bidirectional optical link between front-end electronics and data processing boards in the computer nodes. The GERI board implements the following functionalities: concentrating and preprocessing of the data stream, filtering of the data according to the BM@N trigger signals and providing an interface for the detector control system (DCS) to configure readout electronics.

GBTX emulator for development and special versions of GBT-based readout chains

Abstract: The GBTX ASIC is a standard solution for providing fast control and data readout for radiation detectors used in HEP experiments. However, it is subject to export control restrictions due to the usage of radiation-hard technology. An FPGA-based GBTX emulator (GBTxEMU) has been developed to enable the development of GBT-based readout chains in countries where the original GBTX cannot be imported. Thanks to utilizing a slightly modified GBT-FGPA core, it maintains basic compatibility with standard GBT-based systems. The GBTxEMU also may be an interesting solution for developing GBT-based readout chains for less demanding experiments.