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Author

Michel Luc Cote

Other affiliations: Synopsys
Bio: Michel Luc Cote is an academic researcher from Cadence Design Systems. The author has contributed to research in topics: Standard cell & Design flow. The author has an hindex of 7, co-authored 15 publications receiving 710 citations. Previous affiliations of Michel Luc Cote include Synopsys.

Papers
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Patent
07 Jun 2002
TL;DR: In this article, a phase shifting layout from an original layout is divided into useful groups, i.e., clusters that can be independently processed, so that the phase shifting process can be performed more rapidly.
Abstract: Definition of a phase shifting layout from an original layout can be time consuming. If the original layout is divided into useful groups, i.e. clusters that can be independently processed, then the phase shifting process can be performed more rapidly. If the shapes on the layout are enlarged, then the overlapping shapes can be grouped together to identify shapes that should be processed together. For large layouts, growing and grouping the shapes can be time consuming. Therefore, an approach that uses bins can speed up the clustering process, thereby allowing the phase shifting to be performed in parallel on multiple computers. Additional efficiencies result if identical clusters are identified and processing time saved so that repeated clusters of shapes only undergo the computationally expensive phase shifter placement and assignment process a single time.

192 citations

Patent
05 Apr 2002
TL;DR: In this paper, the authors present a system that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size, and the system then identifies problem areas in the simulated printed image that do not meet a specification.
Abstract: One embodiment of the invention provides a system that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size. During operation, the system receives a representation of a target layout for the integrated circuit, wherein the representation defines a plurality of shapes that comprise the target layout. Next, the system simulates effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout. The system then identifies problem areas in the simulated printed image that do not meet a specification. Next, the system moves corresponding shapes in the target layout to produce a new target layout for the integrated circuit, so that a simulated printed image of the new target layout meets the specification.

192 citations

Patent
23 Sep 2002
TL;DR: In this paper, the authors proposed a method to perform optical proximity correction (OPC) during a noncritical time, e.g. early in cell library development, possibly years prior to the direct application of OPC to a final layout.
Abstract: Performing optical proximity correction (OPC) is typically done during a critical time, wherein even small delays in finishing OPC can have significant adverse effects on product introduction and/or market exposure. In accordance with one feature of the invention, sets of repeating structures in library elements and/or layout data can be identified during a noncritical time, e.g. early in cell library development, possibly years prior to the direct application of OPC to a final layout. OPC can be performed on repeating structures during this noncritical time. Later, during the critical time (e.g. during tape out), an OPC tool can use the pre-processed structures in conjunction with a chip layout to more quickly generate a modified layout, thereby saving valuable time as a chip moves from design to production.

170 citations

Proceedings ArticleDOI
10 Mar 2006
TL;DR: In this article, the authors present a new technique and methodology that overcomes these hurdles and meets both the designer and manufacturing requirements by providing a genuine design for manufacturing (DFM) solution for designers should provide a fast, easy to use and cost-effective solution that accurately predicts the designs sensitivity to shape variations through out the design process.
Abstract: The design of integrated circuits (ICs) has been made possible by a simple contract between design and manufacturing: Manufacturing teams encapsulated their process capabilities into a set of design rules such as minimum width and spacing or overlap for each layer, and designers complied with these design rules to get a manufacturable IC. However, since the advent of 130nm technology, designers have to play by the new rules of sub-90nm technologies. The simple design rules have evolved into extremely complex, context-dependent rules. Minimum design rules have been augmented with many levels of yield-driven recommended guidelines. One of the main drivers behind these complex rules is the increase in optical proximity effects that are directly impacting systematic and parametric yields for sub-90nm designs. A design's sensitivity to optical proximity effects increases as features get smaller, however design engineers do not have visibility into the manufacturability of these features. A genuine design for manufacturing (DFM) solution for designers should provide a fast, easy-to-use and cost-effective solution that accurately predicts the designs sensitivity to shape variations through out the design process. It should identify and reduce design sensitivity by predicting and reducing shape variations. The interface between manufacturing and design must provide designers with the right information to allow them to maximize the manufacturability of their design while shielding them from the effects of resolution enhancement technologies (RET) and manufacturing complexity. This solution should also protect the manufacturing know-how in the case of a fabless foundry flow. Currently, the interface between manufacturing and design solely relies on design rules that do not provide these capabilities. A common proposition for design engineers in predicting shape variation is to move the entire RET/OPC/ORC into the hands of the designer. However, this approach has several major practicality issues that make it unfeasible, even as a "service" offered to designers: 1- Cost associated with replicating the flow on designer's desktop. 2- The ability of designers to understand RET/OPC and perform lithographic judgments. 3- Confidentiality of the recipes and lithographic settings, especially when working with a foundry. 4- The level of confidence the fab/foundry side has in accepting the resulting RET/OPC. 5- Runtime and data volume explosion. 6- The logistics of reflecting RET/OPC and manufacturing changes. 7- The ability to tie this capability to EDA optimization tools. In this paper we present a new technique and methodology that overcomes these hurdles and meets both the designer and manufacturing requirements by providing a genuine DFM solution to designers. We outline a new manufacturing-to-design interface that has evolved from rule-based to model-based, and provides the required visibility to the designer on their design manufacturability. This approach is similar to other EDA approaches which have been used to successfully capture complex behavior by using a formulation that has a higher level of abstraction (for example, SPICE for transistor behavior). We will present how this unique approach uses this abstracted model to provide very accurate prediction of shape variations and at the same time, meet the runtime requirements for a smooth integration into the design flow at 90nm and below. This DFM technology enables designers to improve their design manufacturability, which reduces RET complexity, reduces mask cost and time to volume, and increases the process window and yield.

71 citations

Proceedings ArticleDOI
22 Jun 2001
TL;DR: This paper presents a methodology targeted for standard-cell or structured-custom design styles that start from standard-cells created in a manner in which all issues regarding generation of AltPSM are effectively considered, and are then used in a typical cell-based (synthesis-automatic place and route) flow to produce design layouts that are ready for cost-effective silicon manufacturing.
Abstract: As the semiconductor industry enters the subwavelength era where silicon features are much smaller that the wavelength of the light used to create them, a number of “subwavelength” technologies such as Optical Proximity Correction (OPC) and Phase-Shifting Masks (PSM) have been introduced to produce integrated circuits (ICs) with acceptable yields. An effective approach to subwavelength IC production includes a combination of these techniques, including OPC and PSM. Nevertheless, as we approach silicon features of 0.10&mgr and below, Alternating PSM (AltPSM) becomes a critical part of the technology portfolio needed to achieve IC requirements. An effective EDA methodology that generates AltPSM ICs must guarantee correct generation of AltPSM layouts, maintain or improve today's design productivity, and leverage existing tools and flows. The implementation of such a methodology becomes more complex as phase shifting is applied to all critical features, including those outside of transistor gates. In this paper, we present a methodology targeted for standard-cell or structured-custom design styles. We also present examples of designs that start from standard-cells created in a manner in which all issues regarding generation of AltPSM are effectively considered, and are used in a typical cell-based (synthesis-Automatic Place & Route) flow to produce design layouts that are ready for cost-effective silicon manufacturing.

34 citations


Cited by
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Journal Article
TL;DR: The phase-shifting mask as mentioned in this paper consists of a normal transmission mask that has been coated with a transparent layer patterned to ensure that the optical phases of nearest apertures are opposite.
Abstract: The phase-shifting mask consists of a normal transmission mask that has been coated with a transparent layer patterned to ensure that the optical phases of nearest apertures are opposite. Destructive interference between waves from adjacent apertures cancels some diffraction effects and increases the spatial resolution with which such patterns can be projected. A simple theory predicts a near doubling of resolution for illumination with partial incoherence σ < 0.3, and substantial improvements in resolution for σ < 0.7. Initial results obtained with a phase-shifting mask patterned with typical device structures by electron-beam lithography and exposed using a Mann 4800 10× tool reveals a 40-percent increase in usuable resolution with some structures printed at a resolution of 1000 lines/mm. Phase-shifting mask structures can be used to facilitate proximity printing with larger gaps between mask and wafer. Theory indicates that the increase in resolution is accompanied by a minimal decrease in depth of focus. Thus the phase-shifting mask may be the most desirable device for enhancing optical lithography resolution in the VLSI/VHSIC era.

705 citations

Patent
06 May 2005
TL;DR: In this article, a system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions is presented.
Abstract: A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

313 citations

Patent
06 Feb 2002
TL;DR: In this paper, techniques for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features, are presented.
Abstract: Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of assist features and proximity correction features. The method includes applying an adjustment to a phase shift mask pattern including a first and a second phase shift window, and a control chrome with a control width, and/or to a trim mask pattern having a trim shape with a trim width based upon one or both of a rule based correction and a model based correction to improve a match between a resulting exposure pattern and a target feature.

241 citations

Patent
18 Feb 2005
TL;DR: In this paper, a system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts through generation of hierarchical design rules which capture localized layout requirements, and these adjusted design rules are then used to perform localized layout manipulation and mask data conversion.
Abstract: A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts through generation of hierarchical design rules which capture localized layout requirements. In contrast to conventional techniques which apply global design rules, the disclosed IC design system and method partition the original design layout into a desired level of granularity based on specified layout and integrated circuit properties. At that localized level, the design rules are adjusted appropriately to capture the critical aspects from a manufacturability standpoint. These adjusted design rules are then used to perform localized layout manipulation and mask data conversion.

228 citations

Patent
08 Mar 2007
TL;DR: In this paper, a linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrodes segments within the linear-gated electrode track, while ensuring adequate electrical isolation between the adjacent linear gated electrode segments.
Abstract: A semiconductor device includes a substrate and a number of diffusion regions defined within the substrate. The diffusion regions are separated from each other by a non-active region of the substrate. The semiconductor device includes a number of linear gate electrode tracks defined to extend over the substrate in a single common direction. Each linear gate electrode track is defined by one or more linear gate electrode segments. Each linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrode segments within the linear gate electrode track, while ensuring adequate electrical isolation between the adjacent linear gate electrode segments.

217 citations