Michihiro Shimizu

Bio: Michihiro Shimizu is an academic researcher. The author has contributed to research in topics: Silicon on insulator & Saturation (chemistry). The author has an hindex of 1, co-authored 2 publications receiving 25 citations.

Self-limiting oxidation of SiGe alloy on silicon-on-insulator wafers

Abstract: Self-limiting oxidation of SiGe alloy on silicon-on-insulator wafers was investigated. For oxidation at 1000°C, oxidation stops completely after a few hours for the Si1−xGex (x=0.068–0.16) layers. For higher initial Ge concentrations of the SiGe layer, the oxidation saturated in a shorter oxidation time, whereas saturation was not observed for the oxidation at 900 and 1100°C. The authors propose a model for self-limiting oxidation, in which the oxidation saturation is governed by an interfacial Ge-rich layer that depends on the oxidation temperature and the initial Ge concentration.

Oxidation Saturation of SiGe Alloy on Silicon-on-Insulator Wafers

Abstract: In the oxidation process of SiGe alloy, oxygen atoms are ejected into the SiGe substrate from the interface between the surface oxide and the SiGe layers. [1] During the oxidation of the SiGe layer on the siliconon-insulator (SOI) substrate, Ge atoms pile up below the interface on the SiGe layer and diffuse towards the buried oxide (BOX) layer. The concentration of Ge in the layers between the top oxide and the BOX layers increases by further oxidation. It is considered that the relaxed and thin SiGe layer of high Ge fraction and low dislocation density could be formed by this Ge-condensation method, because the Ge concentration in the initial SiGe layer is low enough to suppress the dislocation and the slippage at the interface on the BOX layer occurs during the condensation.

Two-dimensional condensation for uniaxially strained semiconductor fins

Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

Formation process of high-purity Ge-on-insulator layers by Ge-condensation technique

Abstract: Formation process of Ge-on-insulator (GOI) layers by Ge condensation with very high purity of Ge is clarified in terms of diffusion behaviors of Si and Ge in a SiGe layer. It is shown that the diffusion behavior affects the Ge condensation process, and the purity of GOI layer can be determined by the relation between oxidation and diffusion of Si. Experimental results support a model of GOI formation that the selective oxidation of Si in SiGe continues until the formation of a GOI layer with the residual Si fraction of less than 0.01%. Based on this model, we quantitatively clarify the reason why GOI layers can reach very low residual Si fraction without oxidizing Ge by calculating the diffusion behavior of Si during the Ge condensation process. As a result, we have found that the thermal diffusion of Si is sufficiently fast so that the selective oxidation of Si can continue during the GOI formation process until the averaged residual Si fraction in the SGOI layer becomes lower than 0.03%, which is essentially consistent with the experimental results. In addition, we have found that, even if the GOI layer is thick, the Ge purity of GOI layer can approach 100% infinitely in principle by enhancing the Si diffusion in SGOI compared to the oxidation rate of SGOI.

Antifuse element utilizing non-planar topology

Abstract: Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region.

Non-Planar Device Having Uniaxially Strained Semiconductor Body and Method of Making Same

Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.

SiGeO layer formation mechanism at the SiGe/oxide interfaces during Ge condensation

Abstract: The letter presents the fabrication processes to realize high Ge content SiGe on insulator using Ge condensation technique with and without intermittent oxide etching. During condensation process with intermittent silicon oxide etching, the formation of an undesirable amorphous SiGeO is observed. This is due to uncontrolled oxidation of silicon when the oxide layer is etched away. In the case of Ge condensation process without oxide etching, the authors could achieve a SiGe layer with 91% Ge concentration. A crystalline SiGeO layer at the interfaces of the top silicon oxide and buried oxide with SiGe was also observed. Possible formation mechanisms of amorphous and crystalline SiGeO are presented. Ge condensation process without SiO2 etching utilizes four steps of oxidation and intermittent annealing cycles at each temperature resulted in Si0.09Ge0.91OI substrate.