Michitaka Kameyama

Bio: Michitaka Kameyama is an academic researcher from Tohoku University. The author has contributed to research in topics: Very-large-scale integration & Logic gate. The author has an hindex of 23, co-authored 342 publications receiving 2613 citations. Previous affiliations of Michitaka Kameyama include University UCINF & Rohm.

A 32*32-bit multiplier using multiple-valued MOS current-mode circuits

Abstract: A 32*32-bit multiplier using multiple-valued current-mode circuits has been fabricated in 2- mu m CMOS technology. For the multiplier based on the radix-4 signed-digit number system, 32*32-bit two's complement multiplication can be performed with only three-stage signed-digit full adders using a binary-tree addition scheme. The chip contains about 23600 transistors and the effective multiplier size is about 3.2*5.2 mm/sup 2/, which is half that of the corresponding binary CMOS multiplier. The multiply time is less than 59 ns. The performance is considered comparable to that of the fastest binary multiplier reported. >

A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic

Abstract: A new multiple-valued current-mode MOS integrated circuit is proposed for high-speed arithmetic systems at low supply voltage. Since a multiple-valued source-coupled logic circuit with dual-rail complementary inputs results in a small signal-voltage swing while providing a constant driving current, the switching speed of the circuit is improved at low supply voltage. As an application to arithmetic systems, a 200 MHz 54/spl times/51-b pipelined multiplier using the proposed circuits with a 1.5 V supply voltage is designed with a 0.8-/spl mu/m standard CMOS technology. The performance of the proposed multiplier is evaluated to be about 1.4 times faster than that of a corresponding binary implementation under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the multiple-valued arithmetic circuit.

A multiplier chip with multiple-valued bidirectional current-mode logic circuits

Abstract: A description is given of a 32*32-bit signed digit multiplier implemented with multiple-valued, bidirectional, current-mode circuits and based on two-microcomputer complementary metal-oxide-semiconductor technology. The multiplier can perform 32-bit two's-complement multiplication with three-stage SD full adders using a binary-tree addition scheme The effective multiplier size in the chip and the power dissipation are almost half that of the corresponding binary CMOS multiplier. The multiply time is comparable to that of the fastest binary multiplier. These results establish the effectiveness of the technology for future very large scale integration. >

Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI

Abstract: A novel nonvolatile logic style, called complementary ferroelectric-capacitor (CFC) logic, is proposed for low-power logic-in-memory VLSI, in which storage elements are distributed over the logic-circuit plane. Standby currents in distributed storage elements can be cut off by using ferroelectric-based nonvolatile storage elements, and the standby power dissipation can be greatly reduced. Since the nonvolatile storage and the switching functions are merged into ferroelectric capacitors by the capacitive coupling effect, reduction of active device counts can be achieved. The use of complementary stored data in coupled ferroelectric capacitors makes it possible to perform a switching operation with small degradation of the nonvolatile charge at a low supply voltage. The restore operation can be performed by only applying the small bias across the ferroelectric capacitor, which reduces the dynamic power dissipation. Applying the proposed circuitry in a fully parallel 32-bit content-addressable memory results in about 2/3 dynamic power reduction and 1/7700 static power reduction with chip size of 1/3, compared to a CMOS implementation using 0.6-/spl mu/m ferroelectric/CMOS.

Reconfigurable parallel VLSI processor for dynamic control of intelligent robots

Abstract: In the sensor feedback control of intelligent robots, the delay time must be reduced for a large number of multiply-additions To reduce the delay time for multi-operand multiply additions, the architecture of the reconfigurable parallel processor is proposed In each PE, a switch circuit (SC) is used to change the connection between multipliers and adders By changing the switch elements in the SC using the very-long-instruction-word (VLIW) control method, the multiply-adders having desired numbers of multipliers can be reconfigured every clock cycle Since the data transfer is performed by the direct connection between multipliers and adders, the overhead for data transfer is greatly reduced In addition, the utilised ratio of the multipliers and the adders is increased The chip evaluation based on 08 /spl mu/m CMOS design rule shows that the delay time for dynamic control of a seven-degrees-of-freedom (DOF) redundant robot manipulator becomes about 10 /spl mu/s which is about 77 times faster than that of a parallel-processor approach using conventional digital signal processors (DSPs)

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

‘Memristive’ switches enable ‘stateful’ logic operations via material implication

Abstract: The authors of the International Technology Roadmap for Semiconductors-the industry consensus set of goals established for advancing silicon integrated circuit technology-have challenged the computing research community to find new physical state variables (other than charge or voltage), new devices, and new architectures that offer memory and logic functions beyond those available with standard transistors. Recently, ultra-dense resistive memory arrays built from various two-terminal semiconductor or insulator thin film devices have been demonstrated. Among these, bipolar voltage-actuated switches have been identified as physical realizations of 'memristors' or memristive devices, combining the electrical properties of a memory element and a resistor. Such devices were first hypothesized by Chua in 1971 (ref. 15), and are characterized by one or more state variables that define the resistance of the switch depending upon its voltage history. Here we show that this family of nonlinear dynamical memory devices can also be used for logic operations: we demonstrate that they can execute material implication (IMP), which is a fundamental Boolean logic operation on two variables p and q such that pIMPq is equivalent to (NOTp)ORq. Incorporated within an appropriate circuit, memristive switches can thus perform 'stateful' logic operations for which the same devices serve simultaneously as gates (logic) and latches (memory) that use resistance instead of voltage or charge as the physical state variable.

Memory devices and applications for in-memory computing

Abstract: Traditional von Neumann computing systems involve separate processing and memory units. However, data movement is costly in terms of time and energy and this problem is aggravated by the recent explosive growth in highly data-centric applications related to artificial intelligence. This calls for a radical departure from the traditional systems and one such non-von Neumann computational approach is in-memory computing. Hereby certain computational tasks are performed in place in the memory itself by exploiting the physical attributes of the memory devices. Both charge-based and resistance-based memory devices are being explored for in-memory computing. In this Review, we provide a broad overview of the key computational primitives enabled by these memory devices as well as their applications spanning scientific computing, signal processing, optimization, machine learning, deep learning and stochastic computing. This Review provides an overview of memory devices and the key computational primitives for in-memory computing, and examines the possibilities of applying this computing approach to a wide range of applications.

A functional MOS transistor featuring gate-level weighted sum and threshold operations

Abstract: A functional MOS transistor is proposed which works more intelligently than a mere switching device. The functional transistor calculates the weighted sum of all input signals at the gate level, and controls the 'on' and 'off' of the transistor based on the result of such a weighted sum operation. Since the function is quite analogous to that of biological neurons, the device is named a neuron MOSFET, or neuMOS (vMOS). The device is composed of a floating gate and multiples of input gates that capacitively interact with the floating gate. As the gate-level sum operation is performed in a voltage mode utilizing the capacitive coupling effect, essentially no power dissipation occurs in the calculation, making the device ideal for ULSI implementation. The basic characteristics of neuron MOSFETs as well as of simple circuit blocks are analyzed based on a simple transistor model and experiments. Making use of its very powerful function, a number of interesting circuit applications are explored. A soft hardware logic circuit implemented by neuMOS transistors is also proposed. >