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Mie Matsuo

Bio: Mie Matsuo is an academic researcher from Toshiba. The author has contributed to research in topics: Graphene oxide paper & Layer (electronics). The author has an hindex of 16, co-authored 41 publications receiving 1086 citations.

Papers
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Patent
31 Oct 2007
TL;DR: In this paper, a multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrategies.
Abstract: A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.

289 citations

Patent
02 Sep 1994
TL;DR: In this article, the authors present a polishing method including the steps of forming a film to be polished on a substrate having a recessed portion in its surface so as to fill at least part of the recessed part, and selectively leaving the rest of the film behind.
Abstract: This invention provides a polishing method including the steps of forming a film to be polished on a substrate having a recessed portion in its surface so as to fill at least the recessed portion, and selectively leaving the film to be polished behind in the recessed portion by polishing the film by using a polishing agent containing polishing particles and a solvent, and having a pH of 7.5 or more. The invention also provides a polishing apparatus including a polishing agent storage vessel for storing a polishing agent, a turntable for polishing an object to be polished, a polishing agent supply pipe for supplying the polishing agent from the polishing agent storage vessel onto the turntable, a polishing object holding jig for holding the object to be polished such that the surface to be polished of the object opposes the turntable, and a polishing agent supply pipe temperature adjusting unit, connected to the polishing agent supply pipe, for adjusting the temperature of the polishing agent.

152 citations

Journal ArticleDOI
TL;DR: In this article, the authors demonstrate the feasibility of ultrahigh-density bumpless interconnect by realizing the ultrafine pitch bonding of Cu electrodes at room temperature by using surface-activated bonding (SAB) method.
Abstract: In this paper, we demonstrate the feasibility of ultrahigh-density bumpless interconnect by realizing the ultrafine pitch bonding of Cu electrodes at room temperature. The bumpless interconnect is a novel concept of bonding technology that enables a narrow bonding pitch of less than 10 /spl mu/m by overcoming the thermal strain problem. In the bumpless structure, two thin layers including an insulator and metallic interconnections on the same surface are bonded at room temperature by the surface-activated bonding (SAB) method. In order to realize the bumpless interconnect, we invented a SAB flip-chip bonder that enabled the alignment accuracy of /spl plusmn/1 /spl mu/m in the high vacuum condition. Moreover, the fabrication process of ultrafine Cu electrodes was developed by using the damascene process and reactive ion beam etching (RIE) process, and the bumpless electrodes of 3 /spl mu/m in diameter, 10 /spl mu/m in pitch, and 60 nm in height were formed. As a result, we succeeded in the interconnection of 100 000 bumpless electrodes with the interfacial resistance of less than 1 m/spl Omega/. An increase of the resistance was considerably small after thermal aging at 150/spl deg/C for 1000 h.

115 citations

Patent
Mie Matsuo1, Haruo Okano1, Nobuo Hayasaka1, Kyoichi Suguro1, Hideshi Miyajima1, Junichi Wada1 
06 Jun 1996
TL;DR: In this paper, a method of manufacturing a semiconductor device is described, including the steps of forming a metal oxide film made of a metal oxide having a decrease in standard free energy smaller than the decrease in free energy of hydrogen oxide or carbon oxide.
Abstract: The present invention provides a method of manufacturing a semiconductor device, including the steps of forming a metal oxide film made of a metal oxide having a decrease in standard free energy smaller than a decrease in standard free energy of hydrogen oxide or of carbon oxide, on an insulating film formed on a semiconductor substrate, forming a metal oxide film pattern by subjecting a treatment to the metal oxide film, and converting said metal oxide pattern into at least one of an electrode and a wiring made of a metal which is a main component constituting the metal oxide, by reducing the metal oxide film pattern at a temperature of 80° to 500° C.

61 citations

Patent
23 Aug 2000
TL;DR: In this paper, a semiconductor substrate and a method for manufacturing the same are provided to form an SOI(Silicon On Insulator) structure without causing cost increase or lowering of reliability.
Abstract: PURPOSE: A semiconductor substrate and a method for manufacturing the same are provided to form an SOI(Silicon On Insulator) structure without causing cost increase or lowering of reliability. CONSTITUTION: A plurality of grooves(4) are made in the surface of a silicon substrate(1) while being arranged two-dimensionally and then the silicon substrate(1) is heat treated to deform the plurality of grooves(4) into one planar cavity.

40 citations


Cited by
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Patent
01 Aug 2008
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

1,501 citations

Patent
26 Nov 2002
TL;DR: In this paper, a metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate, so that the process provides vertical wafer-level integration of the devices.
Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

342 citations

Patent
23 Sep 2011
TL;DR: In this article, the dopant species is delivered to the film between the cycles of adsorption and reaction in a surface-mediated reaction, where a film is grown over one or more cycles of reaction.
Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by intermittent delivery of dopant species to the film between the cycles of adsorption and reaction.

341 citations

Patent
22 Nov 2004
TL;DR: In this paper, the authors proposed a method for improved adhesion and oxidation resistance of carbon-containing layers without the need for an additional deposited layer, which can be used in a variety of layers such as barrier layers, etch stops, ARCs, passivation layers, and dielectric layers.
Abstract: The present invention generally provides improved adhesion and oxidation resistance of carbon-containing layers without the need for an additional deposited layer. In one aspect, the invention treats an exposed surface of carbon-containing material, such as silicon carbide, with an inert gas plasma, such as a helium (He), argon (Ar), or other inert gas plasma, or an oxygen-containing plasma such as a nitrous oxide (N 2 O) plasma. Other carbon-containing materials can include organic polymeric materials, amorphous carbon, amorphous fluorocarbon, carbon containing oxides, and other carbon-containing materials. The plasma treatment is preferably performed in situ following the deposition of the layer to be treated. Preferably, the processing chamber in which in situ deposition and plasma treatment occurs is configured to deliver the same or similar precursors for the carbon-containing layer(s). However, the layer(s) can be deposited with different precursors. The invention also provides processing regimes that generate the treatment plasma and systems which use the treatment plasma. The carbon-containing material can be used in a variety of layers, such as barrier layers, etch stops, ARCs, passivation layers, and dielectric layers.

339 citations

Patent
20 Apr 2005
TL;DR: In this article, an apparatus and method of rerouting redistribution lines from an active surface of a semiconductor substrate to a back surface thereof and assembling and packaging individual and multiple semiconductor dice with such rerouted redistribution lines formed thereon is presented.
Abstract: An apparatus and method of rerouting redistribution lines from an active surface of a semiconductor substrate to a back surface thereof and assembling and packaging individual and multiple semiconductor dice with such rerouted redistribution lines formed thereon. The semiconductor substrate includes one or more vias having conductive material formed therein and which extend from an active surface to a back surface of the semiconductor substrate. The redistribution lines are patterned on the back surface of the semiconductor substrate, extending from the conductive material in the vias to predetermined locations on the back surface of the semiconductor substrate that correspond with an interconnect pattern of another substrate for interconnection thereto.

334 citations